ALTERA_CORDIC IP Core User Guide

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ID 683808
Date 5/08/2017
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Document Table of Contents
Document Table of Contents x
1. ALTERA_CORDIC IP Core User Guide
1. ALTERA_CORDIC IP Core User Guide x
1.1. ALTERA_CORDIC IP Core Features 1.2. DSP IP Core Device Family Support 1.3. ALTERA_CORDIC IP Core Functional Description 1.4. ALTERA_CORDIC IP Core Parameters 1.5. ALTERA_CORDIC IP Core Signals
1.3. ALTERA_CORDIC IP Core Functional Description x
1.3.1. SinCos Function 1.3.2. Atan2 Function 1.3.3. Vector Translate Function 1.3.4. Vector Rotate Function
1. ALTERA_CORDIC IP Core User Guide

1.1. ALTERA_CORDIC IP Core Features

  • Supports fixed-point implementations.
  • Supports both latency and frequency driven IP cores.
  • Supports both VHDL and Verilog HDL code generation.
  • Produces fully unrolled implementations.
  • Produces faithfully rounded results to either of the two closest representable numbers in the output.
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