Clock Control Intel® FPGA IP Core Release Notes

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ID 683802
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Clock Control Intel FPGA IP Core Release Notes ( Stratix® 10 Devices) 2. Clock Control Intel FPGA IP Core Release Notes ( Agilex™ Devices)
1. Clock Control Intel FPGA IP Core Release Notes ( Stratix® 10 Devices) x
1.1. Clock Control Intel FPGA IP v20.0.0 1.2. Clock Control Intel FPGA IP v19.1.0 1.3. Clock Control Intel Stratix 10 FPGA IP v18.0 1.4. Stratix 10 Clock Control v17.1 1.5. Stratix® 10 Clocking and PLL User Guide Archives
2. Clock Control Intel FPGA IP Core Release Notes ( Agilex™ Devices) x
2.1. Clock Control Intel FPGA IP v2.0.1 2.2. Clock Control Intel FPGA IP v2.0.0 2.3. Clock Control Intel FPGA IP v1.0.0 2.4. Agilex™ 7 Clocking and PLL User Guide: F-Series and I-Series Archives
1. Clock Control Intel FPGA IP Core Release Notes ( Stratix® 10 Devices)
2. Clock Control Intel FPGA IP Core Release Notes ( Agilex™ Devices)

1.1. Clock Control Intel FPGA IP v20.0.0

Table 1.  v20.0.0 2020.09.28
Quartus® Prime Version Description Impact
20.3
  • Updated the SDC for the clock divider to specify master clocks and exclusive clock groups.
  • Allow IP to be connected within the Platform Designer using the standard Platform Designer interfaces.
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