Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example User Guide

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ID 683800
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example User Guide

4. Document Revision History for Interlaken (2nd Generation) Intel Agilex® 7 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.12.04 23.4 21.1.3

Added support for Questa*-Intel® FPGA Edition simulator.
2023.06.26 23.2 21.1.1

  • Added VHDL support for synthesis and simulation model.

  • Updated product family name to "Intel Agilex® 7".
2022.08.03 21.3 20.0.1 Corrected the device OPN for the Intel Agilex F-Series Transceiver-SoC Development Kit.
2021.10.04 21.3 20.0.1
  • Added support for QuestaSim* simulator.
  • Removed support for NCSim simulator.
2021.02.24 20.4 20.0.1
  • Added information about preserving the unused transceiver channel for PAM4 in section: Hardware Design Example Components.
  • Added the pll_ref_clk[1] signal description in section: Interface Signals.
2020.12.14 20.4 20.0.0
  • Updated sample hardware test output for Interlaken mode and Interlaken Look-aside mode in section Testing the Hardware Design Example.
  • Updated register map for Interlaken Look-aside design example in section Register Map.
  • Added a passing criteria for a successful hardware test run in section Testing the Hardware Design Example.
2020.10.16 20.2 19.3.0 Corrected command to run the initial adaptation calibration on RX side in Testing the Hardware Design Example section.
2020.06.22 20.2 19.3.0
  • The design example is available for Interlaken Look-aside mode.
  • Hardware testing of the design example is available for Intel Agilex device variations.
  • Added Figure: High-level Block Diagram for Interlaken (2nd Generation) Design Example.
  • Updated following sections:
    • Hardware and Software Requirements
    • Directory Structure
  • Modified the following figures to include Interlaken Look-aside related update:
    • Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations
    • Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations
  • Updated Figure: IP Parameter Editor.
  • Added information about the frequency settings in the clock control application in section Compiling and Configuring the Design Example in Hardware.
  • Added test run outputs for the Interlaken Look-aside in the following sections:
    • Simulating the Design Example Testbench
    • Testing the Hardware Design Example
  • Added following new signals in Interface Signals section:
    • mgmt_clk
    • rx_pin_n
    • tx_pin_n
    • mac_clk_pll_ref
  • Added register map for Interlaken Look-aside design example in section: Register Map.
2019.09.30 19.3 19.2.1 Removed clk100. The mgmt_clk serves as a reference clock to the IO PLL in the following:
  • Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations.
  • Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations.
2019.07.01 19.2 19.2 Initial release.
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