Visible to Intel only — GUID: sss1405408463225
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ISP Clamp
When a normal ISP operation begins on a MAX® II or MAX® V device, all I/O pins are tri-stated and weakly pulled up to VCCIO with internal pull-up resistors.
On Intel® MAX® 10 devices, the following behavior applies.
- When normal ISP operation begins on a supported device or when Enable real-time ISP to allow background programming when available in Intel® Quartus® Prime Programmer is unchecked, all I/O pins are tri-stated without pull-up.
- When Enable real-time ISP to allow background programming when available in Intel® Quartus® Prime Programmer is checked, all I/O pins are tri-stated with pull-up.
However, there are situations when the I/O pins of the device should not be tri-stated when the device is in ISP operation. For example, in a running system, some signals such as output enable or chip enable signals might use some of the I/O pins and require those I/O pins to assume a high or low logic level, or maintain their current state when the device is in ISP mode.
In the supported devices, the ISP clamp feature allows you to use the Intel® Quartus® Prime software to hold each I/O pin of a device to a static state when you program the device. After you successfully program the device in ISP clamp mode, the I/O pins are released and the device functions according to the new design.
You can use this feature to indicate that the device is undergoing a programming operation. When the device enters ISP clamp mode, set a particular pin to a state different than the state in the user mode operation of the device.