Arria 10 FPLL IP Core Release Notes

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ID 683784
Date 10/31/2016
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1. Arria 10 FPLL IP Core Release Notes
1. Arria 10 FPLL IP Core Release Notes x
1.1. Arria 10 FPLL IP Core Revision History v16.1 Revision History 1.2. Arria 10 FPLL IP Core Revision History v15.1 Revision History 1.3. Arria 10 FPLL IP Core Revision History v15.0 Revision History 1.4. Arria 10 FPLL IP Core Revision History v14.1 Revision History 1.5. Arria 10 FPLL IP Core Revision History v14.0 Revision History 1.6. Arria 10 FPLL IP Core Revision History v13.1 Revision History
1. Arria 10 FPLL IP Core Release Notes

1.3. Arria 10 FPLL IP Core Revision History v15.0 Revision History

Table 3.  v15.0 May 2015
Description Impact

Changed the following GUI warning: Warning (10858): Verilog HDL warning at altera_xcvr_fpll_a10.sv(487): object pll_extfb_wire used but never assigned.

This compile warning resulted from a dangling net left behind when the CGB master was not generated (enabled). Tied off the pll_extfb_wire signal when the CGB master is not generated to drive it.

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Added an Advanced Parameters tab that displays the following values:

  • C counters (0 to 3)
  • L, M and N counters
  • K fractional division
  • VCO frequency
 -
Truncated the return vco frequency (MHz) to six digits after the decimal point. -
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