Intel® FPGA Voltage Sensor IP Core User Guide

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ID 683781
Date 2/09/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® FPGA Voltage Sensor IP Core Overview 2. Intel® FPGA Voltage Sensor IP Core Getting Started 3. Intel® FPGA Voltage Sensor IP Core Functional Description 4. Intel® FPGA Voltage Sensor IP Core Interface Signals 5. Intel® FPGA Voltage Sensor IP Core Registers 6. Intel® FPGA Voltage Sensor IP Core Implementation Guide 7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide
2. Intel® FPGA Voltage Sensor IP Core Getting Started x
2.1. Specifying Parameters and Options 2.2. Intel® FPGA Voltage Sensor Parameters
3. Intel® FPGA Voltage Sensor IP Core Functional Description x
3.1. Voltage Sensor Controller Core 3.2. Sample Storage Core 3.3. Configuring the Voltage Sensor Controller
3.1. Voltage Sensor Controller Core x
3.1.1. Conversion Modes
3.1.1. Conversion Modes x
3.1.1.1. One Round Conversion 3.1.1.2. Continuous Conversion
3.3. Configuring the Voltage Sensor Controller x
3.3.1. Configuring the Voltage Sensor Controller with Avalon-MM Sample Storage 3.3.2. Configuring the Voltage Sensor Controller with External Sample Storage
4. Intel® FPGA Voltage Sensor IP Core Interface Signals x
4.1. CSR Interface 4.2. Response Interface 4.3. Interrupt Interface
5. Intel® FPGA Voltage Sensor IP Core Registers x
5.1. Voltage Controller Core Registers 5.2. Sample Store Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide x
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
6.1. Using Voltage Sensor in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access 6.1.2. Voltage Sensor Transfer Function
6.1.1. Accessing the Voltage Sensor Using FPGA Core Access x
6.1.1.1. Configuration Registers for the Core Access Mode
6.1.1.1. Configuration Registers for the Core Access Mode x
6.1.1.1.1. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11 6.1.1.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is Equal to 2'b11
1. Intel® FPGA Voltage Sensor IP Core Overview
2. Intel® FPGA Voltage Sensor IP Core Getting Started
3. Intel® FPGA Voltage Sensor IP Core Functional Description
4. Intel® FPGA Voltage Sensor IP Core Interface Signals
5. Intel® FPGA Voltage Sensor IP Core Registers
6. Intel® FPGA Voltage Sensor IP Core Implementation Guide
7. Document Revision History for Intel® FPGA Voltage Sensor IP Core User Guide

4.2. Response Interface

The interface type is Avalon-ST.

Table 5.  Response Interface
Signal Width Description
response_valid 1 Indicates from the source port that current data is valid.
response_channel[2:0] 3

Indicates which channel the voltage sample data corresponds to.

  • Bits 16:8 — not used.
  • Bits 7:0 — Channel 7 to Channel 0.
response_data[5:0] 6 Voltage sample data.
response_startofpacket 1 When asserted, indicates the start of a packet.
response_endofpacket 1 When asserted, indicates the last cycle of a packet.
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