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Answers to Top FAQs
1. Signal Integrity Analysis with Third-Party Tools
2. Reviewing Printed Circuit Board Schematics with the Quartus® Prime Software
3. Siemens EDA PCB Design Tools Support
4. Cadence Board Design Tools Support
5. Quartus® Prime Pro Edition User Guide: PCB Design Tools Document Archives
A. Quartus® Prime Pro Edition User Guides
1.4.1. IBIS Model Access and Customization Flows
1.4.2. Elements of an IBIS Model
1.4.3. Customizing IBIS Models
1.4.4. Design Simulation Using the Siemens EDA HyperLynx* Software
1.4.5. Configuring LineSim to Use Intel IBIS Models
1.4.6. Integrating Intel IBIS Models into LineSim Simulations
1.4.7. Running and Interpreting LineSim Simulations
1.5.1. Supported Devices and Signaling
1.5.2. Accessing HSPICE Simulation Kits
1.5.3. The Double Counting Problem in HSPICE Simulations
1.5.4. HSPICE Writer Tool Flow
1.5.5. Running an HSPICE Simulation
1.5.6. Interpreting the Results of an Output Simulation
1.5.7. Interpreting the Results of an Input Simulation
1.5.8. Viewing and Interpreting Tabular Simulation Results
1.5.9. Viewing Graphical Simulation Results
1.5.10. Making Design Adjustments Based on HSPICE Simulations
1.5.11. Sample Input for I/O HSPICE Simulation Deck
1.5.12. Sample Output for I/O HSPICE Simulation Deck
1.5.13. Advanced Topics
1.5.12.1. Header Comment
1.5.12.2. Simulation Conditions
1.5.12.3. Simulation Options
1.5.12.4. Constant Definition
1.5.12.5. I/O Buffer Netlist
1.5.12.6. Drive Strength
1.5.12.7. Slew Rate and Delay Chain
1.5.12.8. I/O Buffer Instantiation
1.5.12.9. Board and Trace Termination
1.5.12.10. Double-Counting Compensation Circuitry
1.5.12.11. Simulation Analysis
2.1. Reviewing Quartus® Prime Software Settings
2.2. Reviewing Device Pin-Out Information in the Fitter Report
2.3. Reviewing Compilation Error and Warning Messages
2.4. Using Additional Quartus® Prime Software Features
2.5. Using Additional Quartus® Prime Software Tools
2.6. Reviewing Printed Circuit Board Schematics with the Quartus® Prime Software Revision History
4.1. Cadence PCB Design Tools Support
4.2. Product Comparison
4.3. FPGA-to-PCB Design Flow
4.4. Setting Up the Quartus® Prime Software
4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software
4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software
4.7. Cadence Board Design Tools Support Revision History
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1.4.6. Integrating Intel IBIS Models into LineSim Simulations
When the location for IBIS files has been set, you can assign the downloaded or generated IBIS models to the buffers in your schematic. To do this, perform the following steps:
- Double-click a buffer symbol in your schematic to open the Assign Models dialog box. You can also click Assign Models from the buffer symbol’s right-click menu.
Figure 7. LineSim Assign Model Dialog Box
- The pin of the buffer symbol you selected should be highlighted in the Pins list. If you want to assign a model to a different symbol or pin, select it from the list.
- Click Select. The Select IC Model dialog box appears.
Figure 8. LineSim Select IC Model Dialog Box
- To filter the list of available libraries to display only IBIS models, select .IBS. Scroll through the Libraries list, and click the name of the library for your design. By default, this is <project name>.ibs.
- The device for your design should be selected as the only item in the Devices list. If not, select your device from the list.
- From the Signal list, select the name of the signal you want to simulate. You can also choose to select by device pin number.
- Click OK. The Assign Models dialog box displays the selected .ibs file and signal.
- If applicable to the signal you chose, adjust the buffer settings as required for the simulation.
- Select and configure other buffer pins from the Pins list in the same manner.
- Click OK when all I/O models are assigned.