Visible to Intel only — GUID: mwh1410471097480
Ixiasoft
Visible to Intel only — GUID: mwh1410471097480
Ixiasoft
1.3.1. Create I/O and Board Trace Model Assignments
To configure a board trace model, specify the board trace model assignment settings for each I/O standard used in your design. You can add series or parallel termination, specify the transmission line length, and set the value of the far-end capacitive load. You can configure these parameters in the Board Trace Model view of the Pin Planner (Assignments > Pin Planner).
The Quartus® Prime software can generate IBIS models and HSPICE decks without having to configure a board trace model. Generated IBIS models ignore any board trace model settings other than the far-end capacitive load. If any load value is set other than the default, the delay given by IBIS models generated by the IBIS Writer cannot be used to account correctly for the double counting problem.
The load value mismatch between the IBIS delay and the tCO measurement of the Quartus® Prime software prevents the delays from being safely added together. Warning messages displayed when the EDA Netlist Writer runs indicate when this mismatch occurs.