Request input parameters.

The IP asserts this signal after reset.

You should provide input parameters when the IP asserts this signal. The IP does not accept input data until you provide input parameters.

Indicates that the IP is ready to accept input parameters.

Ready latency is 1 clock cycle. If this signal is asserted, the IP takes the valid signal (param_valid) in the next clock cycle.

The IP asserts this signal before each code block.

The IP asserts this signal when the IP asserts param_req.

If the IP asserts this signal but not param_req, you can optionally provide input parameters. If you do not provide input parameters, the IP keeps the previous parameters.

Assert when incoming packet parameter signals are valid.

Assert this signal for one clock cycle when param_ready is asserted. If asserted for more than one cycle, the IP takes only the parameters at the first cycle.

1:N=32

2:N=64

3:N=128

4:N=256

5:N=512

6:N=1024

0:CRC OFF

1:CRC24a

2:CRC24b

3:CRC24c

4:CRC16

5:CRC11

6:CRC6

7:CRC24c in DCI format

0:deinterleaving off

1:deinterleaving on

Indicates frozen bit location.

param_fro[i]==1 indicates bit i is a frozen bit.

param_fro[1023:N] are ignored when N<1024.

Indicates parity check bit location.

param_pc[i]==1 indicates the i-th information bit is a parity check bit.

param_pc[j] is ignored if the number of information bits is less than j.

param_pc[0] should always be zero.

k-th information bit is never a parity check bit for all k>=28.

Indicates the radio network temporary identifier (RNTI) bits.

When you do not select CRC type as CRC24c in DCI format (3’d7), the IP ignores the RNTI.

Indicates that the IP can take an input packet.

Ready latency is 1 clock cycle. If the IP asserts this signal, the IP takes the valid signal (sink_valid) in the next clock cycle.

When asserted, this signal keeps asserted until the end of the input packet.

Assert when incoming packet data signal is valid.

The IP accepts this signal only when the IP asserts sink_ready in the previous clock cycle.

When this signal is low, the IP ignores sink_sop, eop, and data.

Do not assert this signal at the next clock cycle of a valid EOP, as the IP ignores it. The IP does not accept SOP immediately after EOP.

Do not assert this signal at the next clock cycle of param_valid, as the IP ignores it. The IP does not accept SOP immediatley after a new parameter setup.

If the IP asserts both param_ready and sink_ready on the previous clock cycle and you assert both param_valid and sink_valid on the current clock cycle, the IP only acepts param_valid and ignores sink_valid.

Indicates the start of an incoming packet.

The IP starts to accept incoming packets when you assert this signal.

Assert this signal with the first input data.

Indicates the end of an incoming packet.

Assert this signal with the last input data.

Frame data input.

The IP asserts source_valid when dumping an output packet, indicating the outputs are valid.

Encoded data output.

The IP sends an N-bit codeword at source_data[N-1:0].

Clock.

Request input parameters.

The IP asserts this signal after reset.

You should provide input parameters when the IP asserts this signal. The IP does not accept input data until you provide input parameters.

The IP can accept input parameters.

Ready latency is 1 clock cycle. If the IP asserts this signal, the IP accepts the valid signal (param_valid) in the next clock cycle.

The IP asserts this signal before each code block.

The IP asserts this signal when it asserts param_req.

If the IP asserts this signal but not param_req, you can optionally provide input parameters. If you provide no input parameters, the IP keeps the previous parameters.

Assert when incoming packet parameter signals are valid.

Assert this signal for one clock cycle when the IP asserts param_ready. If asserted for more than one cycle, the IP accepts only the parameters at the first cycle.

1:N=32

2:N=64

3:N=128

4:N=256

5:N=512

6:N=1024

0:CRC OFF

1:CRC24a

2:CRC24b

3:CRC24c

4:CRC16

5:CRC11

6:CRC6

7:CRC24c in DCI format

0:deinterleaving off

1:deinterleaving on

Indicate frozen bit location.

param_fro[i]==1 indicates bit i is a frozen bit.

param_fro[1023:N] are ignored when N<1024.

Indicate parity check bit location.

param_pc[i]==1 indicates the i-th information bit is a parity check bit.

param_pc[j] is ignored if the number of information bits is less than j.

param_pc[0] should always be set to zero.

k-th information bit is never a parity check bit for all k>=28.

Indicates the RNTI bits.

When you do not select CRC type as CRC24c in DCI format (3’d7), the IP ignores the RNTI.

Indicates that the IP can accept an input packet.

The ready latency is 1 clock cycle. If the IP asserts this signal, the IP accepts the valid signal (sink_valid) in the next clock cycle.

When asserted, this signal keeps asserted until the end of the input packet.

Assert when incoming packet data signal is valid.

The IP accepts this signal only when the IP asserts sink_ready in the previous clock cycle.

When this signal is low, the IP ignores sink_sop/eop/data.

Do not assert this signal at the next clock cycle of a valid EOP, as the IP ignores it. The IP does not accept SOP immediately after EOP.

Do not assert this signal at the next clock cycle of param_valid, as the IP ignores it. The IP does not accept SOP immediatley after a new parameter setup.

If the IP asserts both param_ready and sink_ready on the previous clock cycle and you assert both param_valid are sink_valid on the current clock cycle, the IP only acepts param_valid and ignores sink_valid.

Indicates the start of an incoming packet.

The IP starts to accept incoming packet when you assert this signal.

Assert this signal for one cycle only.

Indicates the end of an incoming packet.

Assert this signal with the last input data.

Assert this signal for one cycle only.

Frame data input.

Each LLR is LLR_BIT-bit long. You should send 64 LLRs in each cycle.

Each packet contains N LLRs of a frame, taking N/64 cycles.

Send LLR[63]-LLR[0] in the first cycle; LLR[127]-LLR[64] in the second cycle, etc.

When N=32, send LLR[31]-LLR[0] in sink_data[32*LLR_BIT-1:0].

2’s compliment format, but exclude the extreme negative values.

LLR ranges from –(2^LLR_BIT-1-1) to +(2^LLR_BIT-1-1). Saturate the value –2^LLR_BIT-1 to –(2^LLR_BIT-1-1) before providing to the IP.

Refer to Table 8

Assert when you can accept an outgoing packet.

The ready latency is 1 clock cycle. When you assert this signal, the IP provides the valid signal (source_valid) in the next clock cycle, if output data is available from the IP.

Asserted when dumping an output packet, indicating the outputs are valid.

The IP can only assert this signal if it receives source_ready in the previous clock cycle.

Indicates the start of an output packet.

After decoding finishes and when the downstream is ready, the IP asserts this signal when it provides the first cycle of the output data.

Indicates the end of an output packet.

The IP asserts this signal when it provides the last cycle of the output data.

Decoded data output. The IP sends out M bits out, where M = number of interleaved bits, M = K - number of parity check bits, and M = number of message bits + number of CRC bits.

For more information, refer to the Inputs to the Encoder table in 5G Polar Functional Description.

The IP sends CRC bits and does not send parity check bits.

The IP sends out[63:0] in the same cycle as source_sop. The IP sends out[127:64] in the cycle after. If M does not divide 64, the IP sends out[M-1: M-(M mod 64)] in the same cycle as source_eop, located at source_data[(M mod 64)-1:0].

An output packet takes ceil(M/64) cycles.

When M<64, out[M-1:0] are located at source_data[M-1:0].

Indicates CRC check result.

0: CRC is OFF or CRC check failed

1: CRC check passed.

This value is valid from source_sop to source_eop and the IP does not change it during this period