Low Latency 100G Ethernet Stratix® 10 FPGA IP Core Release Notes

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ID 683755
Date 8/05/2024
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1. Low Latency 100G Ethernet Stratix® 10 FPGA IP Core Release Notes
1. Low Latency 100G Ethernet Stratix® 10 FPGA IP Core Release Notes x
1.1. Low Latency 100G Ethernet Stratix® 10 FPGA IP Core v22.2.0 1.2. Low Latency 100G Ethernet Stratix® 10 FPGA IP Core v18.1 1.3. Low Latency 100G Ethernet Stratix® 10 FPGA IP Core v18.0 1.4. Stratix® 10 Low Latency 100G Ethernet IP Core v17.1
1. Low Latency 100G Ethernet Stratix® 10 FPGA IP Core Release Notes

1.3. Low Latency 100G Ethernet Stratix® 10 FPGA IP Core v18.0

Table 3.  Version 18.0
Description Impact Notes

Added support for local fault and remote fault monitoring and statistics.

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Added support for optional IEEE 802.3 Clause 31 Ethernet flow control and priority-based flow control.

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Added support for 322.265625 MHz PHY reference frequency.

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Transceiver reconfiguration clock and control and status interface clock changed from 100 - 125 MHz to 100 - 162 MHz.

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Added parameters for Low Latency 100G Ethernet Intel FPGA IP core:
  • Enable MAC Flow Control - Turning on this parameter enables the flow control mechanism.
  • Number of queues in priority flow control - Number of distinct priority queues for priority-based flow control.
  • Enable link fault generation - Turning on this parameter includes link fault signaling modules and relevant signals.
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Added support for hardware design example generation using Stratix 10 GX Transceiver Signal Integrity Development Kit.

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