| Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores. |
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| Added support for PCS-Direct mode. The PCS-Direct mode enables you to bypass all the internal PCS blocks. |
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| Changed the maximum data rate supported by GT channels to 28300 Mbps. |
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| Added support for Embedded debug feature. This feature enables you to write to the PLL control registers and read from status registers for the PLL instances in the design. This feature is available under the Dynamic Reconfiguration tab. |
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| Changed Enable embedded JTAG AVMM Master parameter to Enable Altera Debug Master Endpoint parameter. |
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Added the following parameters:
- PMA Configuration Rules.
- Enable fast sync status reporting for deterministic latency SM under the Word Aligner and Bitslip tab. Use this parameter for implementing CPRI (Auto) protocol.
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| Added Faster Register mode for PCS TX and RX FIFO. |
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| Changed the parameter Enable Reconfiguration between Standard and Enhanced PCS to Enable Datapath and Interface Reconfiguration. |
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| Changed the one-time option for CTLE and DFE adaptation mode to Triggered mode. |
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| Removed Enable tx_enh_fifo_cnt port and Enable rx_enh_fifo_cnt port parameters from the IP Parameter Editor. |
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| Removed the parameter Device Speed Gradeselection. |
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| Removed 62.5, 125, 200, and 250 values for PPM detector threshold. |
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| Enhanced user warnings and information messages. |
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Added the following presets:
- 3G SDI NTSC
- 3G SDI PAL
- HD SDI NTSC
- HD SDI PAL
- Low Latency GT
- SAS Gen1
- SAS Gen1.1
- SAS Gen2
- SATA Gen1
- SATA Gen2
- SATA Gen3
- SFI-S 64:64 4x11.3Gbps
- SONET/SDH OC-12
- SONET/SDH OC-48
- SONET/SDH OC-96
- Serial Rapid IO 1.25Gbps
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