External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 11/28/2024
Public
Document Table of Contents

4.1.2.28. ctrl_amm for DDR4

Controller Avalon Memory-Mapped interface

Table 76.  Interface: ctrl_ammInterface type: Avalon Memory-Mapped Slave
Port Name Direction Description
amm_ready Output Ready signal is asserted when the controller can accept commands, and is de-asserted when controller is busy
amm_read Input Read request signal
amm_write Input Write request signal
amm_address Input Address for the read/write request
amm_readdata Output Read data
amm_writedata Input Write data
amm_burstcount Input Number of transfers in each read/write burst
amm_byteenable Input Byte-enable for write data
amm_beginbursttransfer Input Indicates when a burst is starting
amm_readdatavalid Output Indicates whether read data is valid