External Memory Interfaces Stratix® 10 FPGA IP User Guide

Download PDF
ID 683741
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Release Information 2. External Memory Interfaces Stratix® 10 FPGA IP Introduction 3. Stratix® 10 EMIF IP Product Architecture 4. Stratix® 10 EMIF IP End-User Signals 5. Stratix® 10 EMIF – Simulating Memory IP 6. Stratix® 10 EMIF IP for DDR3 7. Stratix® 10 EMIF IP for DDR4 8. Stratix® 10 EMIF IP for QDR II/II+/II+ Xtreme 9. Stratix® 10 EMIF IP for QDR-IV 10. Stratix® 10 EMIF IP for RLDRAM 3 11. Stratix® 10 EMIF IP Timing Closure 12. Optimizing Controller Performance 13. Stratix® 10 EMIF IP Debugging 14. External Memory Interfaces Stratix® 10 FPGA IP User Guide Archives 15. Document Revision History for External Memory Interfaces Stratix® 10 FPGA IP User Guide
2. External Memory Interfaces Stratix® 10 FPGA IP Introduction x
2.1. Stratix® 10 EMIF IP Design Flow 2.2. Stratix® 10 EMIF IP Design Checklist
3. Stratix® 10 EMIF IP Product Architecture x
3.1. Stratix® 10 EMIF Architecture: Introduction 3.2. Stratix® 10 EMIF Sequencer 3.3. Stratix® 10 EMIF Calibration 3.4. Intel Stratix 10 EMIF IP Controller 3.5. Hardware Resource Sharing Among Multiple Stratix® 10 EMIFs 3.6. User-requested Reset in Stratix® 10 EMIF IP 3.7. Stratix® 10 EMIF for Hard Processor Subsystem 3.8. Stratix® 10 EMIF Ping Pong PHY
3.1. Stratix® 10 EMIF Architecture: Introduction x
3.1.1. Stratix® 10 EMIF Architecture: I/O Subsystem 3.1.2. Stratix® 10 EMIF Architecture: I/O Column 3.1.3. Stratix® 10 EMIF Architecture: I/O SSM 3.1.4. Stratix® 10 EMIF Architecture: I/O Bank 3.1.5. Stratix® 10 EMIF Architecture: I/O Lane 3.1.6. Stratix® 10 EMIF Architecture: Input DQS Clock Tree 3.1.7. Stratix® 10 EMIF Architecture: PHY Clock Tree 3.1.8. Stratix® 10 EMIF Architecture: PLL Reference Clock Networks 3.1.9. Stratix® 10 EMIF Architecture: Clock Phase Alignment
3.2. Stratix® 10 EMIF Sequencer x
3.2.1. Stratix® 10 EMIF DQS Tracking
3.3. Stratix® 10 EMIF Calibration x
3.3.1. Stratix® 10 Calibration Stages 3.3.2. Stratix® 10 Calibration Stages Descriptions 3.3.3. Stratix® 10 Calibration Flowchart 3.3.4. Stratix® 10 Calibration Algorithms Address and Command Calibration Read Calibration Write Calibration
3.4. Intel Stratix 10 EMIF IP Controller x
3.4.1. Hard Memory Controller 3.4.2. Stratix® 10 Hard Memory Controller Rate Conversion Feature
3.4.1. Hard Memory Controller x
3.4.1.1. Hard Memory Controller Features 3.4.1.2. Hard Memory Controller Main Control Path 3.4.1.3. Data Buffer Controller
3.5. Hardware Resource Sharing Among Multiple Stratix® 10 EMIFs x
3.5.1. I/O SSM Sharing 3.5.2. I/O Bank Sharing 3.5.3. PLL Reference Clock Sharing 3.5.4. Core Clock Network Sharing
3.7. Stratix® 10 EMIF for Hard Processor Subsystem x
3.7.1. Restrictions on I/O Bank Usage for Stratix® 10 EMIF IP with HPS 3.7.2. Using the Legacy EMIF Debug Toolkit with Stratix® 10 HPS Interfaces 3.7.3. HPS EMIF Simulation
3.8. Stratix® 10 EMIF Ping Pong PHY x
3.8.1. Stratix® 10 Ping Pong PHY Feature Description 3.8.2. Stratix® 10 Ping Pong PHY Architecture 3.8.3. Stratix® 10 Ping Pong PHY Limitations 3.8.4. Stratix® 10 Ping Pong PHY Calibration 3.8.5. Using the Ping Pong PHY 3.8.6. Ping Pong PHY Simulation Example Design
4. Stratix® 10 EMIF IP End-User Signals x
4.1. Interface and Signal Descriptions 4.2. AFI Signals 4.3. AFI 4.0 Timing Diagrams 4.4. Stratix® 10 Memory Mapped Register (MMR) Tables
4.1. Interface and Signal Descriptions x
4.1.1. Intel Stratix 10 EMIF IP Interfaces for DDR3 4.1.2. Intel Stratix 10 EMIF IP Interfaces for DDR4 4.1.3. Intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ Xtreme 4.1.4. Intel Stratix 10 EMIF IP Interfaces for QDR-IV 4.1.5. Intel Stratix 10 EMIF IP Interfaces for RLDRAM 3
4.1.1. Intel Stratix 10 EMIF IP Interfaces for DDR3 x
4.1.1.1. local_reset_req for DDR3 4.1.1.2. local_reset_status for DDR3 4.1.1.3. pll_ref_clk for DDR3 4.1.1.4. pll_locked for DDR3 4.1.1.5. pll_extra_clk_0 for DDR3 4.1.1.6. pll_extra_clk_1 for DDR3 4.1.1.7. pll_extra_clk_2 for DDR3 4.1.1.8. pll_extra_clk_3 for DDR3 4.1.1.9. oct for DDR3 4.1.1.10. mem for DDR3 4.1.1.11. status for DDR3 4.1.1.12. afi_reset_n for DDR3 4.1.1.13. afi_clk for DDR3 4.1.1.14. afi_half_clk for DDR3 4.1.1.15. afi for DDR3 4.1.1.16. emif_usr_reset_n for DDR3 4.1.1.17. emif_usr_clk for DDR3 4.1.1.18. emif_usr_reset_n_sec for DDR3 4.1.1.19. emif_usr_clk_sec for DDR3 4.1.1.20. cal_debug_reset_n for DDR3 4.1.1.21. cal_debug_clk for DDR3 4.1.1.22. cal_debug_out_reset_n for DDR3 4.1.1.23. cal_debug_out_clk for DDR3 4.1.1.24. clks_sharing_master_out for DDR3 4.1.1.25. clks_sharing_slave_in for DDR3 4.1.1.26. clks_sharing_slave_out for DDR3 4.1.1.27. ctrl_amm for DDR3 4.1.1.28. ctrl_auto_precharge for DDR3 4.1.1.29. ctrl_user_priority for DDR3 4.1.1.30. ctrl_ecc_user_interrupt for DDR3 4.1.1.31. ctrl_ecc_readdataerror for DDR3 4.1.1.32. ctrl_ecc_status for DDR3 4.1.1.33. ctrl_mmr_slave for DDR3 4.1.1.34. hps_emif for DDR3 4.1.1.35. cal_debug for DDR3 4.1.1.36. cal_debug_out for DDR3
4.1.2. Intel Stratix 10 EMIF IP Interfaces for DDR4 x
4.1.2.1. local_reset_req for DDR4 4.1.2.2. local_reset_status for DDR4 4.1.2.3. pll_ref_clk for DDR4 4.1.2.4. pll_locked for DDR4 4.1.2.5. pll_extra_clk_0 for DDR4 4.1.2.6. pll_extra_clk_1 for DDR4 4.1.2.7. pll_extra_clk_2 for DDR4 4.1.2.8. pll_extra_clk_3 for DDR4 4.1.2.9. ac_parity_err for DDR4 4.1.2.10. oct for DDR4 4.1.2.11. mem for DDR4 4.1.2.12. status for DDR4 4.1.2.13. afi_reset_n for DDR4 4.1.2.14. afi_clk for DDR4 4.1.2.15. afi_half_clk for DDR4 4.1.2.16. afi for DDR4 4.1.2.17. emif_usr_reset_n for DDR4 4.1.2.18. emif_usr_clk for DDR4 4.1.2.19. emif_usr_reset_n_sec for DDR4 4.1.2.20. emif_usr_clk_sec for DDR4 4.1.2.21. cal_debug_reset_n for DDR4 4.1.2.22. cal_debug_clk for DDR4 4.1.2.23. cal_debug_out_reset_n for DDR4 4.1.2.24. cal_debug_out_clk for DDR4 4.1.2.25. clks_sharing_master_out for DDR4 4.1.2.26. clks_sharing_slave_in for DDR4 4.1.2.27. clks_sharing_slave_out for DDR4 4.1.2.28. ctrl_amm for DDR4 4.1.2.29. ctrl_auto_precharge for DDR4 4.1.2.30. ctrl_user_priority for DDR4 4.1.2.31. ctrl_ecc_user_interrupt for DDR4 4.1.2.32. ctrl_ecc_readdataerror for DDR4 4.1.2.33. ctrl_ecc_status for DDR4 4.1.2.34. ctrl_mmr_slave for DDR4 4.1.2.35. hps_emif for DDR4 4.1.2.36. cal_debug for DDR4 4.1.2.37. cal_debug_out for DDR4
4.1.3. Intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ Xtreme x
4.1.3.1. local_reset_req for QDR II/II+/II+ Xtreme 4.1.3.2. local_reset_status for QDR II/II+/II+ Xtreme 4.1.3.3. pll_ref_clk for QDR II/II+/II+ Xtreme 4.1.3.4. pll_locked for QDR II/II+/II+ Xtreme 4.1.3.5. pll_extra_clk_0 for QDR II/II+/II+ Xtreme 4.1.3.6. pll_extra_clk_1 for QDR II/II+/II+ Xtreme 4.1.3.7. pll_extra_clk_2 for QDR II/II+/II+ Xtreme 4.1.3.8. pll_extra_clk_3 for QDR II/II+/II+ Xtreme 4.1.3.9. oct for QDR II/II+/II+ Xtreme 4.1.3.10. mem for QDR II/II+/II+ Xtreme 4.1.3.11. status for QDR II/II+/II+ Xtreme 4.1.3.12. emif_usr_reset_n for QDR II/II+/II+ Xtreme 4.1.3.13. emif_usr_clk for QDR II/II+/II+ Xtreme 4.1.3.14. cal_debug_reset_n for QDR II/II+/II+ Xtreme 4.1.3.15. cal_debug_clk for QDR II/II+/II+ Xtreme 4.1.3.16. cal_debug_out_reset_n for QDR II/II+/II+ Xtreme 4.1.3.17. cal_debug_out_clk for QDR II/II+/II+ Xtreme 4.1.3.18. clks_sharing_master_out for QDR II/II+/II+ Xtreme 4.1.3.19. clks_sharing_slave_in for QDR II/II+/II+ Xtreme 4.1.3.20. clks_sharing_slave_out for QDR II/II+/II+ Xtreme 4.1.3.21. ctrl_amm for QDR II/II+/II+ Xtreme 4.1.3.22. cal_debug for QDR II/II+/II+ Xtreme 4.1.3.23. cal_debug_out for QDR II/II+/II+ Xtreme
4.1.4. Intel Stratix 10 EMIF IP Interfaces for QDR-IV x
4.1.4.1. local_reset_req for QDR-IV 4.1.4.2. local_reset_status for QDR-IV 4.1.4.3. pll_ref_clk for QDR-IV 4.1.4.4. pll_locked for QDR-IV 4.1.4.5. pll_extra_clk_0 for QDR-IV 4.1.4.6. pll_extra_clk_1 for QDR-IV 4.1.4.7. pll_extra_clk_2 for QDR-IV 4.1.4.8. pll_extra_clk_3 for QDR-IV 4.1.4.9. oct for QDR-IV 4.1.4.10. mem for QDR-IV 4.1.4.11. status for QDR-IV 4.1.4.12. afi_reset_n for QDR-IV 4.1.4.13. afi_clk for QDR-IV 4.1.4.14. afi_half_clk for QDR-IV 4.1.4.15. afi for QDR-IV 4.1.4.16. emif_usr_reset_n for QDR-IV 4.1.4.17. emif_usr_clk for QDR-IV 4.1.4.18. cal_debug_reset_n for QDR-IV 4.1.4.19. cal_debug_clk for QDR-IV 4.1.4.20. cal_debug_out_reset_n for QDR-IV 4.1.4.21. cal_debug_out_clk for QDR-IV 4.1.4.22. clks_sharing_master_out for QDR-IV 4.1.4.23. clks_sharing_slave_in for QDR-IV 4.1.4.24. clks_sharing_slave_out for QDR-IV 4.1.4.25. ctrl_amm for QDR-IV 4.1.4.26. cal_debug for QDR-IV 4.1.4.27. cal_debug_out for QDR-IV
4.1.5. Intel Stratix 10 EMIF IP Interfaces for RLDRAM 3 x
4.1.5.1. local_reset_req for RLDRAM 3 4.1.5.2. local_reset_status for RLDRAM 3 4.1.5.3. pll_ref_clk for RLDRAM 3 4.1.5.4. pll_locked for RLDRAM 3 4.1.5.5. pll_extra_clk_0 for RLDRAM 3 4.1.5.6. pll_extra_clk_1 for RLDRAM 3 4.1.5.7. pll_extra_clk_2 for RLDRAM 3 4.1.5.8. pll_extra_clk_3 for RLDRAM 3 4.1.5.9. oct for RLDRAM 3 4.1.5.10. mem for RLDRAM 3 4.1.5.11. status for RLDRAM 3 4.1.5.12. afi_reset_n for RLDRAM 3 4.1.5.13. afi_clk for RLDRAM 3 4.1.5.14. afi_half_clk for RLDRAM 3 4.1.5.15. afi for RLDRAM 3 4.1.5.16. cal_debug_reset_n for RLDRAM 3 4.1.5.17. cal_debug_clk for RLDRAM 3 4.1.5.18. cal_debug_out_reset_n for RLDRAM 3 4.1.5.19. cal_debug_out_clk for RLDRAM 3 4.1.5.20. clks_sharing_master_out for RLDRAM 3 4.1.5.21. clks_sharing_slave_in for RLDRAM 3 4.1.5.22. clks_sharing_slave_out for RLDRAM 3 4.1.5.23. cal_debug for RLDRAM 3 4.1.5.24. cal_debug_out for RLDRAM 3
4.2. AFI Signals x
4.2.1. AFI Clock and Reset Signals 4.2.2. AFI Address and Command Signals 4.2.3. AFI Write Data Signals 4.2.4. AFI Read Data Signals 4.2.5. AFI Calibration Status Signals 4.2.6. AFI Shadow Register Management Signals
4.3. AFI 4.0 Timing Diagrams x
4.3.1. AFI Address and Command Timing Diagrams 4.3.2. AFI Write Sequence Timing Diagrams 4.3.3. AFI Read Sequence Timing Diagrams 4.3.4. AFI Calibration Status Timing Diagram
4.4. Stratix® 10 Memory Mapped Register (MMR) Tables x
4.4.1. ctrlcfg0 4.4.2. ctrlcfg1 4.4.3. dramtiming0 4.4.4. caltiming0 4.4.5. caltiming1 4.4.6. caltiming2 4.4.7. caltiming3 4.4.8. caltiming4 4.4.9. caltiming9 4.4.10. dramaddrw 4.4.11. sideband0 4.4.12. sideband1 4.4.13. sideband4 4.4.14. sideband6 4.4.15. sideband7 4.4.16. sideband9 4.4.17. sideband11 4.4.18. sideband12 4.4.19. sideband13 4.4.20. sideband14 4.4.21. dramsts 4.4.22. niosreserve0 4.4.23. niosreserve1 4.4.24. sideband16 4.4.25. ecc3: ECC Error and Interrupt Configuration 4.4.26. ecc4: Status and Error Information 4.4.27. ecc5: Address of Most Recent SBE/DBE 4.4.28. ecc6: Address of Most Recent Correction Command Dropped 4.4.29. ecc7: Extension for Address of Most Recent SBE/DBE 4.4.30. ecc8: Extension for Address of Most Recent Correction Command Dropped
5. Stratix® 10 EMIF – Simulating Memory IP x
5.1. Simulation Options 5.2. HPS EMIF Simulation 5.3. Simulation Walkthrough
5.3. Simulation Walkthrough x
5.3.1. Calibration Modes 5.3.2. Abstract PHY Simulation 5.3.3. Simulation Scripts 5.3.4. Functional Simulation with Verilog HDL 5.3.5. Functional Simulation with VHDL 5.3.6. Simulating the Design Example
5.3.6. Simulating the Design Example x
5.3.6.1. User-requested Reset in Stratix® 10 EMIF IP
6. Stratix® 10 EMIF IP for DDR3 x
6.1. Parameter Descriptions 6.2. Register Map IP-XACT Support for Stratix® 10 EMIF DDR3 IP 6.3. Board Skew Equations 6.4. Pin and Resource Planning 6.5. DDR3 Board Design Guidelines
6.1. Parameter Descriptions x
6.1.1. Intel Stratix 10 EMIF IP DDR3 Parameters: General 6.1.2. Intel Stratix 10 EMIF IP DDR3 Parameters: Memory 6.1.3. Intel Stratix 10 EMIF IP DDR3 Parameters: Mem I/O 6.1.4. Intel Stratix 10 EMIF IP DDR3 Parameters: FPGA I/O 6.1.5. Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Timing 6.1.6. Intel Stratix 10 EMIF IP DDR3 Parameters: Board 6.1.7. Intel Stratix 10 EMIF IP DDR3 Parameters: Controller 6.1.8. Intel Stratix 10 EMIF IP DDR3 Parameters: Diagnostics 6.1.9. Intel Stratix 10 EMIF IP DDR3 Parameters: Example Designs
6.3. Board Skew Equations x
6.3.1. Equations for DDR3 Board Skew Parameters
6.4. Pin and Resource Planning x
6.4.1. Interface Pins 6.4.2. FPGA Resources 6.4.3. Pin Guidelines for Stratix® 10 EMIF IP
6.4.1. Interface Pins x
6.4.1.1. Estimating Pin Requirements 6.4.1.2. DIMM Options 6.4.1.3. Maximum Number of Interfaces
6.4.2. FPGA Resources x
6.4.2.1. OCT 6.4.2.2. PLL
6.4.3. Pin Guidelines for Stratix® 10 EMIF IP x
6.4.3.1. General Guidelines 6.4.3.2. x4 DIMM Implementation 6.4.3.3. Command and Address Signals 6.4.3.4. Clock Signals 6.4.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals 6.4.3.6. Resource Sharing Guidelines (Multiple Interfaces) 6.4.3.7. Ping-Pong PHY Implementation
6.5. DDR3 Board Design Guidelines x
6.5.1. Terminations and Slew Rates with Stratix® 10 Devices 6.5.2. Channel Signal Integrity Measurement 6.5.3. Layout Approach 6.5.4. Design Layout Guidelines 6.5.5. Package Deskew
6.5.1. Terminations and Slew Rates with Stratix® 10 Devices x
6.5.1.1. Dynamic On-Chip Termination (OCT) in Stratix® 10 Devices 6.5.1.2. Choosing Terminations on Stratix® 10 Devices 6.5.1.3. On-Chip Termination Recommendations for Stratix® 10 Devices 6.5.1.4. Slew Rates
6.5.2. Channel Signal Integrity Measurement x
6.5.2.1. Importance of Accurate Channel Signal Integrity Information 6.5.2.2. Understanding Channel Signal Integrity Measurement 6.5.2.3. How to Enter Calculated Channel Signal Integrity Values 6.5.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity
6.5.4. Design Layout Guidelines x
6.5.4.1. General Layout Guidelines 6.5.4.2. Layout Guidelines 6.5.4.3. Length Matching Rules 6.5.4.4. Spacing Guidelines 6.5.4.5. Fly-By Network Design for Clock, Command, and Address Signals
6.5.5. Package Deskew x
6.5.5.1. DQ/DQS/DM Deskew 6.5.5.2. Address and Command Deskew 6.5.5.3. Package Deskew Recommendations for Stratix® 10 Devices 6.5.5.4. Deskew Example 6.5.5.5. Package Migration
7. Stratix® 10 EMIF IP for DDR4 x
7.1. Parameter Descriptions 7.2. Register Map IP-XACT Support for Stratix® 10 EMIF DDR4 IP 7.3. Board Skew Equations 7.4. Pin and Resource Planning 7.5. DDR4 Board Design Guidelines
7.1. Parameter Descriptions x
7.1.1. Intel Stratix 10 EMIF IP DDR4 Parameters: General 7.1.2. Intel Stratix 10 EMIF IP DDR4 Parameters: Memory 7.1.3. Intel Stratix 10 EMIF IP DDR4 Parameters: Mem I/O 7.1.4. Intel Stratix 10 EMIF IP DDR4 Parameters: FPGA I/O 7.1.5. Intel Stratix 10 EMIF IP DDR4 Parameters: Mem Timing 7.1.6. Intel Stratix 10 EMIF IP DDR4 Parameters: Board 7.1.7. Intel Stratix 10 EMIF IP DDR4 Parameters: Controller 7.1.8. Intel Stratix 10 EMIF IP DDR4 Parameters: Diagnostics 7.1.9. Intel Stratix 10 EMIF IP DDR4 Parameters: Example Designs
7.3. Board Skew Equations x
7.3.1. Equations for DDR4 Board Skew Parameters
7.4. Pin and Resource Planning x
7.4.1. Interface Pins 7.4.2. FPGA Resources 7.4.3. Pin Guidelines for Stratix® 10 EMIF IP 7.4.4. Resource Sharing Guidelines (Multiple Interfaces)
7.4.1. Interface Pins x
7.4.1.1. Estimating Pin Requirements 7.4.1.2. DIMM Options 7.4.1.3. Maximum Number of Interfaces
7.4.2. FPGA Resources x
7.4.2.1. OCT 7.4.2.2. PLL
7.4.3. Pin Guidelines for Stratix® 10 EMIF IP x
7.4.3.1. General Guidelines 7.4.3.2. x4 DIMM Implementation 7.4.3.3. Command and Address Signals 7.4.3.4. Clock Signals 7.4.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals 7.4.3.6. alert_n Pin Termination Recommendation
7.5. DDR4 Board Design Guidelines x
7.5.1. Terminations and Slew Rates with Stratix® 10 Devices 7.5.2. Channel Signal Integrity Measurement 7.5.3. Layout Approach 7.5.4. Design Layout Guidelines 7.5.5. Package Deskew
7.5.1. Terminations and Slew Rates with Stratix® 10 Devices x
7.5.1.1. Dynamic On-Chip Termination (OCT) in Stratix® 10 Devices 7.5.1.2. Dynamic On-Die Termination (ODT) in DDR4 7.5.1.3. Choosing Terminations on Stratix® 10 Devices 7.5.1.4. On-Chip Termination Recommendations for Stratix® 10 Devices 7.5.1.5. Slew Rates
7.5.2. Channel Signal Integrity Measurement x
7.5.2.1. Importance of Accurate Channel Signal Integrity Information 7.5.2.2. Understanding Channel Signal Integrity Measurement 7.5.2.3. How to Enter Calculated Channel Signal Integrity Values 7.5.2.4. Guidelines for Calculating DDR4 Channel Signal Integrity
7.5.4. Design Layout Guidelines x
7.5.4.1. General Layout Guidelines 7.5.4.2. Layout Guidelines 7.5.4.3. Length Matching Rules 7.5.4.4. Spacing Guidelines 7.5.4.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) 7.5.4.6. Fly-By Network Design for Clock, Command, and Address Signals 7.5.4.7. Clamshell Topology 7.5.4.8. Additional Layout Guidelines for DDR4 Twin-die Devices
7.5.5. Package Deskew x
7.5.5.1. DQ/DQS/DM Deskew 7.5.5.2. Address and Command Deskew 7.5.5.3. Package Deskew Recommendations for Stratix® 10 Devices 7.5.5.4. Deskew Example 7.5.5.5. Package Migration
8. Stratix® 10 EMIF IP for QDR II/II+/II+ Xtreme x
8.1. Parameter Descriptions 8.2. Board Skew Equations 8.3. Pin and Resource Planning 8.4. QDR II/II+/II+ Xtreme Board Design Guidelines
8.1. Parameter Descriptions x
8.1.1. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: General 8.1.2. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Memory 8.1.3. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA I/O 8.1.4. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Timing 8.1.5. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Board 8.1.6. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Controller 8.1.7. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Diagnostics 8.1.8. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Example Designs
8.2. Board Skew Equations x
8.2.1. Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Parameters
8.3. Pin and Resource Planning x
8.3.1. Interface Pins
8.3.1. Interface Pins x
8.3.1.1. Estimating Pin Requirements 8.3.1.2. Maximum Number of Interfaces 8.3.1.3. FPGA Resources 8.3.1.4. OCT 8.3.1.5. PLL 8.3.1.6. Pin Guidelines for Stratix® 10 EMIF IP
8.3.1.6. Pin Guidelines for Stratix® 10 EMIF IP x
8.3.1.6.1. General Guidelines 8.3.1.6.2. QDR II, QDR II+ and QDR II+ Xtreme SRAM Command Signals 8.3.1.6.3. QDR II, QDR II+ and QDR II+ Xtreme SRAM Address Signals 8.3.1.6.4. QDR II, QDR II+, and QDR II+ Xtreme SRAM Clock Signals 8.3.1.6.5. QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD Signals 8.3.1.6.6. Resource Sharing Guidelines (Multiple Interfaces)
8.4. QDR II/II+/II+ Xtreme Board Design Guidelines x
8.4.1. QDR II SRAM Configurations 8.4.2. General Layout Guidelines 8.4.3. QDR II Layout Guidelines 8.4.4. QDR II SRAM Layout Approach 8.4.5. Package Deskew 8.4.6. Package Migration 8.4.7. Slew Rates
9. Stratix® 10 EMIF IP for QDR-IV x
9.1. Parameter Descriptions 9.2. Board Skew Equations 9.3. Pin and Resource Planning 9.4. QDR-IV Board Design Guidelines
9.1. Parameter Descriptions x
9.1.1. Intel Stratix 10 EMIF IP QDR-IV Parameters: General 9.1.2. Intel Stratix 10 EMIF IP QDR-IV Parameters: Memory 9.1.3. Intel Stratix 10 EMIF IP QDR-IV Parameters: FPGA I/O 9.1.4. Intel Stratix 10 EMIF IP QDR-IV Parameters: Mem Timing 9.1.5. Intel Stratix 10 EMIF IP QDR-IV Parameters: Board 9.1.6. Intel Stratix 10 EMIF IP QDR-IV Parameters: Controller 9.1.7. Intel Stratix 10 EMIF IP QDR-IV Parameters: Diagnostics 9.1.8. Intel Stratix 10 EMIF IP QDR-IV Parameters: Example Designs
9.2. Board Skew Equations x
9.2.1. Equations for QDR-IV Board Skew Parameters
9.3. Pin and Resource Planning x
9.3.1. Interface Pins
9.3.1. Interface Pins x
9.3.1.1. Estimating Pin Requirements 9.3.1.2. Maximum Number of Interfaces 9.3.1.3. FPGA Resources 9.3.1.4. OCT 9.3.1.5. PLL 9.3.1.6. Pin Guidelines for Stratix® 10 EMIF IP 9.3.1.7. Resource Sharing Guidelines (Multiple Interfaces)
9.3.1.6. Pin Guidelines for Stratix® 10 EMIF IP x
9.3.1.6.1. General Guidelines 9.3.1.6.2. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 9.3.1.6.3. QDR IV SRAM Clock Signals 9.3.1.6.4. QDR IV SRAM Data, DINV, and QVLD Signals
9.4. QDR-IV Board Design Guidelines x
9.4.1. QDR-IV Layout Approach 9.4.2. General Layout Guidelines 9.4.3. QDR-IV Layout Guidelines 9.4.4. Package Deskew 9.4.5. Package Migration 9.4.6. Slew Rates
10. Stratix® 10 EMIF IP for RLDRAM 3 x
10.1. Parameter Descriptions 10.2. Board Skew Equations 10.3. Pin and Resource Planning 10.4. RLDRAM 3 Board Design Guidelines
10.1. Parameter Descriptions x
10.1.1. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: General 10.1.2. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Memory 10.1.3. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: FPGA I/O 10.1.4. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem Timing 10.1.5. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Board 10.1.6. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Diagnostics 10.1.7. Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Example Designs
10.2. Board Skew Equations x
10.2.1. Equations for RLDRAM 3 Board Skew Parameters
10.3. Pin and Resource Planning x
10.3.1. Interface Pins
10.3.1. Interface Pins x
10.3.1.1. Estimating Pin Requirements 10.3.1.2. Maximum Number of Interfaces 10.3.1.3. FPGA Resources 10.3.1.4. OCT 10.3.1.5. PLL 10.3.1.6. Pin Guidelines for Stratix® 10 EMIF IP 10.3.1.7. Resource Sharing Guidelines (Multiple Interfaces)
10.3.1.6. Pin Guidelines for Stratix® 10 EMIF IP x
10.3.1.6.1. General Guidelines 10.3.1.6.2. RLDRAM 3 Commands and Addresses 10.3.1.6.3. RLDRAM 3 Clock Signals 10.3.1.6.4. RLDRAM 3 Data, DM and QVLD Signals
10.4. RLDRAM 3 Board Design Guidelines x
10.4.1. RLDRAM 3 Configurations 10.4.2. General Layout Guidelines 10.4.3. RLDRAM 3 Layout Guidelines 10.4.4. Layout Approach 10.4.5. Package Deskew 10.4.6. Package Migration 10.4.7. Slew Rates
11. Stratix® 10 EMIF IP Timing Closure x
11.1. Timing Closure 11.2. Timing Report DDR 11.3. Optimizing Timing 11.4. Early I/O Timing Estimation
11.1. Timing Closure x
11.1.1. Timing Analysis
11.1.1. Timing Analysis x
11.1.1.1. PHY or Core 11.1.1.2. I/O Timing
11.1.1.2. I/O Timing x
11.1.1.2.1. Read Capture 11.1.1.2.2. Write 11.1.1.2.3. Address and Command 11.1.1.2.4. DQS Gating / Postamble 11.1.1.2.5. Write Leveling
11.4. Early I/O Timing Estimation x
11.4.1. Performing Early I/O Timing Analysis
12. Optimizing Controller Performance x
12.1. Interface Standard 12.2. Bank Management Efficiency 12.3. Data Transfer 12.4. Improving Controller Efficiency
12.4. Improving Controller Efficiency x
12.4.1. Auto-Precharge Commands 12.4.2. Latency 12.4.3. Calibration 12.4.4. Bank Interleaving 12.4.5. Additive Latency and Bank Interleaving 12.4.6. User-Controlled Refresh 12.4.7. Frequency of Operation 12.4.8. Series of Reads or Writes 12.4.9. Data Reordering 12.4.10. Starvation Control 12.4.11. Command Reordering 12.4.12. Bandwidth 12.4.13. Enable Command Priority Control
12.4.2. Latency x
12.4.2.1. Additive Latency
12.4.6. User-Controlled Refresh x
12.4.6.1. Back-to-Back User-Controlled Refresh Usage
13. Stratix® 10 EMIF IP Debugging x
13.1. Interface Configuration Performance Issues 13.2. Functional Issue Evaluation 13.3. Timing Issue Characteristics 13.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer 13.5. Hardware Debugging Guidelines 13.6. Categorizing Hardware Issues 13.7. Debugging Stratix® 10 EMIF IP 13.8. Using the Default Traffic Generator 13.9. Using the Configurable Traffic Generator (TG2)
13.1. Interface Configuration Performance Issues x
13.1.1. Interface Configuration Bottleneck and Efficiency Issues
13.2. Functional Issue Evaluation x
13.2.1. Intel® IP Memory Model 13.2.2. Vendor Memory Model 13.2.3. Transcript Window Messages 13.2.4. Modifying the Example Driver to Replicate the Failure
13.3. Timing Issue Characteristics x
13.3.1. Evaluating FPGA Timing Issues 13.3.2. Evaluating External Memory Interface Timing Issues
13.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer x
13.4.1. Signals to Monitor with the Signal Tap II Logic Analyzer
13.5. Hardware Debugging Guidelines x
13.5.1. Create a Simplified Design that Demonstrates the Same Issue 13.5.2. Measure Power Distribution Network 13.5.3. Measure Signal Integrity and Setup and Hold Margin 13.5.4. Vary Voltage 13.5.5. Operate at a Lower Speed 13.5.6. Determine Whether the Issue Exists in Previous Versions of Software 13.5.7. Determine Whether the Issue Exists in the Current Version of Software 13.5.8. Try A Different PCB 13.5.9. Try Other Configurations 13.5.10. Debugging Checklist
13.6. Categorizing Hardware Issues x
13.6.1. Signal Integrity Issues 13.6.2. Hardware and Calibration Issues
13.6.1. Signal Integrity Issues x
13.6.1.1. Characteristics of Signal Integrity Issues 13.6.1.2. Evaluating SignaI Integrity Issues
13.6.1.2. Evaluating SignaI Integrity Issues x
13.6.1.2.1. Skew 13.6.1.2.2. Crosstalk 13.6.1.2.3. Power System 13.6.1.2.4. Clock Signals 13.6.1.2.5. Read Data Valid Window and Eye Diagram 13.6.1.2.6. Write Data Valid Window and Eye Diagram 13.6.1.2.7. OCT and ODT Usage
13.6.2. Hardware and Calibration Issues x
13.6.2.1. Postamble Timing Issues and Margin 13.6.2.2. Intermittent Issue Evaluation
13.7. Debugging Stratix® 10 EMIF IP x
13.7.1. Debugging With the Legacy External Memory Interface Debug Toolkit 13.7.2. Debugging with the External Memory Interface Unified Calibration Debug Toolkit 13.7.3. On-Chip Debug Port for Stratix® 10 EMIF IP 13.7.4. Legacy Efficiency Monitor and Protocol Checker 13.7.5. New Efficiency Monitor
13.7.1. Debugging With the Legacy External Memory Interface Debug Toolkit x
13.7.1.1. User Interface 13.7.1.2. Communication 13.7.1.3. Setup and Use 13.7.1.4. Configuring Your EMIF IP for Use with the Legacy Debug Toolkit 13.7.1.5. Reports 13.7.1.6. On-Die Termination Calibration 13.7.1.7. Eye Diagram 13.7.1.8. Driver Margining for Stratix® 10 EMIF IP 13.7.1.9. Example Tcl Script for Running the Legacy EMIF Debug Toolkit 13.7.1.10. Using the Legacy EMIF Debug Toolkit with Stratix® 10 HPS Interfaces
13.7.1.4. Configuring Your EMIF IP for Use with the Legacy Debug Toolkit x
13.7.1.4.1. Daisy-Chaining Additional EMIF IP Cores for Debugging 13.7.1.4.2. General Workflow 13.7.1.4.3. Linking the Project to a Device 13.7.1.4.4. Establishing Communication to Connections 13.7.1.4.5. Selecting an Active Interface
13.7.1.8. Driver Margining for Stratix® 10 EMIF IP x
13.7.1.8.1. Determining Margin
13.7.2. Debugging with the External Memory Interface Unified Calibration Debug Toolkit x
13.7.2.1. Prerequisites for Using the EMIF Unified Calibration Debug Toolkit 13.7.2.2. Configuring a Design to use the EMIF Unified Calibration Debug Toolkit 13.7.2.3. Launching the EMIF Debug Toolkit 13.7.2.4. Using the EMIF Debug Toolkit 13.7.2.5. Exporting Tables 13.7.2.6. Viewing Diagrams in the Eye Viewer 13.7.2.7. Guidelines for Debugging Calibration Issues
13.7.2.2. Configuring a Design to use the EMIF Unified Calibration Debug Toolkit x
13.7.2.2.1. Generating a Design Example with the Debug Toolkit 13.7.2.2.2. Adding Interfaces to an Design Example 13.7.2.2.3. Enabling the EMIF Unified Calibration Debug Toolkit in an Existing Design
13.7.2.4. Using the EMIF Debug Toolkit x
13.7.2.4.1. Memory Configuration Tab 13.7.2.4.2. Calibration Tab 13.7.2.4.3. Calibration Report Tab 13.7.2.4.4. Calibrate Termination Tab 13.7.2.4.5. Vref Margining Tab 13.7.2.4.6. Driver Margining Tab 13.7.2.4.7. ISSP Tab 13.7.2.4.8. Pin Delay Settings Tab
13.7.2.7. Guidelines for Debugging Calibration Issues x
13.7.2.7.1. Debugging Calibration Failure Using Information from the Calibration report 13.7.2.7.2. Debugging Address and Command Leveling Calibration Failure 13.7.2.7.3. Debugging Address and Command Deskew Failure 13.7.2.7.4. Debugging DQS Enable Failure 13.7.2.7.5. Debugging Read Deskew Calibration Failure 13.7.2.7.6. Debugging VREFIN Calibration Failure 13.7.2.7.7. Debugging LFIFO Calibration Failure 13.7.2.7.8. Debugging Write Leveling Failure 13.7.2.7.9. Debugging Write Deskew Calibration Failure 13.7.2.7.10. Debugging VREFOUT Calibration Failure
13.7.3. On-Chip Debug Port for Stratix® 10 EMIF IP x
13.7.3.1. EMIF On-Chip Debug Port 13.7.3.2. Access Protocol
13.7.4. Legacy Efficiency Monitor and Protocol Checker x
13.7.4.1. Including the Legacy Efficiency Monitor and Protocol Checker in Your Generated IP 13.7.4.2. Running the Legacy Efficiency Monitor with the External Memory Debug Toolkit 13.7.4.3. Communicating Directly to the Legacy Efficiency Monitor and Protocol Checker
13.7.5. New Efficiency Monitor x
13.7.5.1. Enabling the Efficiency Monitor in a Design Example 13.7.5.2. Efficiency Monitor Block Descriptions 13.7.5.3. Control and Status Registers 13.7.5.4. Opening the Efficiency Monitor
13.8. Using the Default Traffic Generator x
13.8.1. Reading the Default Traffic Generator Status 13.8.2. Running Infinite Traffic using the Default Traffic Generator 13.8.3. Changing the Reset Trigger of the Default Traffic Generator 13.8.4. Observing Generated Traffic with Signal Tap
13.9. Using the Configurable Traffic Generator (TG2) x
13.9.1. Enabling the Traffic Generator in a Design Example 13.9.2. Traffic Generator Block Description 13.9.3. Default Traffic Pattern 13.9.4. Configuration and Status Registers 13.9.5. User Pattern 13.9.6. Traffic Generator Status 13.9.7. Starting Traffic with the Traffic Generator 13.9.8. Traffic Generator Configuration User Interface 13.9.9. Examples of Configuring the TG2 Traffic Generator
13.9.5. User Pattern x
13.9.5.1. Test Duration / Instruction pattern 13.9.5.2. Address Pattern 13.9.5.3. Data Pattern and Byte Enable
13.9.5.2. Address Pattern x
13.9.5.2.1. Address Generator Modes 13.9.5.2.2. Address Generator MSB Indices 13.9.5.2.3. Address Generator Effective Width 13.9.5.2.4. Address Generator Relative Frequencies 13.9.5.2.5. Address Pattern Examples - Basic Mode 13.9.5.2.6. Address Pattern Examples - Advanced Mode
13.9.8. Traffic Generator Configuration User Interface x
13.9.8.1. Connecting the Traffic Generator 13.9.8.2. Claiming and Releasing the TG Config Interface 13.9.8.3. Configuring the Traffic Generator 13.9.8.4. Traffic Generator Preset Selection 13.9.8.5. Traffic Generator Status Report
1. Release Information
2. External Memory Interfaces Stratix® 10 FPGA IP Introduction
3. Stratix® 10 EMIF IP Product Architecture
4. Stratix® 10 EMIF IP End-User Signals
5. Stratix® 10 EMIF – Simulating Memory IP
6. Stratix® 10 EMIF IP for DDR3
7. Stratix® 10 EMIF IP for DDR4
8. Stratix® 10 EMIF IP for QDR II/II+/II+ Xtreme
9. Stratix® 10 EMIF IP for QDR-IV
10. Stratix® 10 EMIF IP for RLDRAM 3
11. Stratix® 10 EMIF IP Timing Closure
12. Optimizing Controller Performance
13. Stratix® 10 EMIF IP Debugging
14. External Memory Interfaces Stratix® 10 FPGA IP User Guide Archives
15. Document Revision History for External Memory Interfaces Stratix® 10 FPGA IP User Guide

3.3.4. Stratix® 10 Calibration Algorithms

The calibration algorithms sometimes vary, depending on the targeted memory protocol.

Address and Command Calibration

Address and command calibration consists of the following parts:
  • Leveling calibration— (DDR3 and DDR4 only) Toggles the CS# and CAS# signals to send read commands while keeping other address and command signals constant. The algorithm monitors for incoming DQS signals, and if the DQS signal toggles, it indicates that the read commands have been accepted. The algorithm then repeats using different delay values, to find the optimal window.

  • Deskew calibration— (DDR4 and QDR-IV only)
    • (DDR4) Uses the DDR4 address and command parity feature. The FPGA sends the address and command parity bit, and the DDR4 memory device responds with an alert signal if the parity bit is detected. The alert signal from the memory device tells the FPGA that the parity bit was received.

      Deskew calibration requires use of the PAR/ALERT# pins, so you should not omit these pins from your design. One limitation of deskew calibration is that it cannot deskew ODT and CKE pins.

    • (QDR-IV) Uses the QDR-IV loopback mode. The FPGA sends address and command signals, and the memory device sends back the address and command signals which it captures, via the read data pins. The returned signals indicate to the FPGA what the memory device has captured. Deskew calibration can deskew all synchronous address and command signals.
      Note: For more information about loopback mode, refer to your QDR-IV memory device data sheet.

Read Calibration

  • DQSen calibration— (DDR3, DDR4, RLDRAMx and QDRx) DQSen calibration occurs before Read deskew, therefore only a single DQ bit is required to pass in order to achieve a successful read pass.
    • (DDR3 and DDR4) The DQSen calibration algorithm searches the DQS preamble using a hardware state machine. The algorithm sends many back-to-back reads with a one clock cycle gap between. The hardware state machine searches for the DQS gap while sweeping DQSen delay values. The algorithm then increments the VFIFO value, and repeats the process until a pattern is found. The process is then repeated for all other read DQS groups.

    • (RLDRAMx and QDRx) The DQSen calibration algorithm does not use a hardware state machine; rather, it calibrates cycle-level delays using software and subcycle delays using DQS tracking hardware. The algorithm requires good data in memory, and therefore relies on guaranteed writes. (Writing a burst of 0s to one location, and a burst of 1s to another; back-to-back reads from these two locations are used for read calibration.)

      The algorithm enables DQS tracking to calibrate the phase component of DQS enable, and then issues a guaranteed write, followed by back-to-back reads. The algorithm sweeps DQSen values cycle by cycle until the read operation succeeds. The process is then repeated for all other read groups.

  • Deskew calibration— Read deskew calibration is performed before write leveling, and must be performed at least twice: once before write calibration, using simple data patterns from guaranteed writes, and again after write calibration, using complex data patterns.

    The deskew calibration algorithm performs a guaranteed write, and then sweeps dqs_in delay values from low to high, to find the right edge of the read window. The algorithm then sweeps dq-in delay values low to high, to find the left edge of the read window. Updated dqs_in and dq_in delay values are then applied to center the read window. The algorithm then repeats the process for all data pins.

  • Vref-In calibration— Read Vref-In calibration begins by programming Vref-In with an arbitrary value. The algorithm then sweeps the Vref-In value from the starting value to both ends, and measures the read window for each value. The algorithm selects the Vref-In value which provides the maximum read window.

  • LFIFO calibration— Read LFIFO calibration normalizes read delays between groups. The PHY must present all data to the controller as a single data bus. The LFIFO latency should be large enough for the slowest read data group, and large enough to allow proper synchronization across FIFOs.

Write Calibration

  • Leveling calibration— Write leveling calibration aligns the write strobe and clock to the memory clock, to compensate for skews. In general, leveling calibration tries a variety of delay values to determine the edges of the write window, and then selects an appropriate value to center the window. The details of the algorithm vary, depending on the memory protocol.
    • (DDRx) Write leveling occurs before write deskew, therefore only one successful DQ bit is required to register a pass. Write leveling staggers the DQ bus to ensure that at least one DQ bit falls within the valid write window.
    • (RLDRAMx) Optimizes for the CK versus DK relationship.
    • (QDR-IV) Optimizes for the CK versus DK relationship. Is covered by address and command deskew using the loopback mode.
    • (QDR II/II+/Xtreme) The K clock is the only clock, therefore write leveling is not required.
  • Deskew calibration— Performs per-bit deskew of write data relative to the write strobe and clock. Write deskew calibration does not change dqs_out delays; the write clock is aligned to the CK clock during write leveling.

  • VREF-Out calibration— (DDR4) Calibrates the VREF level at the memory device. The VREF-Out calibration algorithm is similar to the VREF-In calibration algorithm.
Level Two Title