AN 908: Enabling 4G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000

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ID 683736
Date 1/30/2020
Public
Document Table of Contents
Document Table of Contents x
1. About the 4G Wireless Acceleration Reference Design 2. 4G User Image Description 3. Document Revision History for AN 908: Enabling 4G Wireless Acceleration in FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000
1. About the 4G Wireless Acceleration Reference Design x
1.1. 4G User Image Features 1.2. About the Intel PAC N3000
1.2. About the Intel PAC N3000 x
1.2.1. Factory Image for 2x2x25 GbE
2. 4G User Image Description x
2.1. User Image Power Management 2.2. 4G Channel Coder 2.3. Fronthaul IO 2.4. User Image Software
2.2. 4G Channel Coder x
2.2.1. 4G Channel Coder Throughput 2.2.2. 4G Turbo-V Encoder and Decoder Tests 2.2.3. 4G VRAN Universal Verification Methodology
2.3. Fronthaul IO x
2.3.1. O-RAN Compression and Decompression
1. About the 4G Wireless Acceleration Reference Design
2. 4G User Image Description
3. Document Revision History for AN 908: Enabling 4G Wireless Acceleration in FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000

2.2.1. 4G Channel Coder Throughput

The Intel FPGA PAC N3000 4G channel coder contains four encoders and six decoders. The throughput depends on the traffic model.

Baseline values include:

  • Max code block size 6,144 downlink, 5,824 uplink
  • Max transport block size 75,376 down and uplink
  • 1 ms TTI
  • Fmax = 275 MHz

Uplink throughput (decoding path) is 10 x (75376 + 13*24 +24) bits in 500 µs, which is 1.5142 Gbits/s @ 8 iterations. The decoders can decode 10 x 13 = 130 code-blocks of length 5,824 bits in 500 µs @ 8 iterations

Downlink throughput (encoding path) is 10 x 2 x (75376 + 13 *24 +24) bits in 333 µs, which is 4.5473 Gbits/s. The encoders can encode 10 x 2 x 13 = 260 code-blocks of length 6,144 bits in 333 µs.

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