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Ixiasoft
Design Example 2: Generating Clock Signals
This design example uses the ALTPLL IP core to generate and modify internal clock signals. This example generates three internal clock signals from an external 100-MHz clock signal.
In this example, you perform the following activities:
- Generate 133 MHz, 200 MHz, and 200 MHz clocks that are time shifted by 1.00 ns from a 100 MHz external input clock using the ALTPLL IP core.
- Implement the shift_clk design by assigning the EP1S10F780 device to the project and compiling the project.
- Simulate the shift_clk design.