ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks

To generate 133-MHz, 200-MHz, and 200-MHz time-shifted clocks, follow these steps:

Download and unzip the shift_clk.zip.

  1. In the Quartus® Prime software, open the project file shift_clk.qpf.
  2. Open the top-level shift_clk.qpf file. You complete this project in this example.
  3. Expand the I/O folder and click ALTPLL.
  4. In Which type of output file do you want to create?, select AHDL.
  5. For What name do you want for the output file?, name the output file as shift_pll.
  6. Click Next. Page 3 appears.
  7. To specify the 100 MHz input clock (inclk0), perform the following steps:
  8. On page 3 of the General section, for What is the frequency of the inclock0 input?, type 100 , and select MHz.
  9. Under PLL type, click Select the PLL type automatically.
  10. In the Operation mode section, select In Normal Mode.
  11. For Which output clock will be compensated for?, select c0.
  12. Click Next. Page 4 appears.
  13. In the Dynamic configuration section, turn off the Create optional inputs for dynamic reconfiguration option.
  14. In the Optional inputs section, perform the following steps:
    1. Turn off Create an ‘pllena’ input to selectively enable the PLL.
    2. Turn off Create an ‘areset’ input to asynchronously reset the PLL.
    3. Turn off Create an ‘pfdena’ input to selectively enable the phase/frequency detector.
  15. In the Lock output section, turn on Create ‘locked’ output.
  16. Leave the other options in the Parameter Settings tab as the default.
  17. To specify the 133 MHz output clock (c0), perform the following steps:
  18. Click the Output Clocks tab to see the output clocks of the PLL. Page 7 appears.
  19. On the clk c0 page, turn on Use this clock.
  20. In the Clock Tap Settings section, perform the following steps:
    1. Turn off Enter output clock frequency.
    2. Turn on Enter output clock parameters.
    3. For Clock multiplication factor, type 4.
    4. For Clock division factor, type 3.
    5. For Clock phase shift, type 0 and select deg.
    6. For Clock duty cycle (%), type 50.00.
  21. Leave the other options at their default values.
  22. Click Next. Page 8 appears.
  23. To specify the 200 MHz output clock (c1), perform the following steps:
  24. On the clk c1 page, turn on Use this clock.
  25. In the Clock Tap Settings section, perform the following steps:
    1. Turn off Enter output clock frequency.
    2. Turn on Enter output clock parameters.
    3. For Clock multiplication factor, type 2.
    4. For Clock division factor, type 1.
    5. For Clock phase shift, type 0.00 and select ns.
    6. For Clock duty cycle (%), type 50.00.
  26. Leave all other options at their default values.
  27. Click Next. Page 9 appears.
  28. To specify the 200 MHz output clock c2 with a 1.00 nanosecond delay, perform the following steps:
  29. On the clk c2 page, turn on Use this clock.
  30. In the Clock Tap Settings section, perform the following steps:
    1. Turn off Enter output clock frequency.
    2. Turn on Enter output clock parameters.
    3. For Clock multiplication factor, type 2.
    4. For Clock division factor, type 1.
    5. For Clock phase shift, type 1.00 and select deg.
    6. For Clock duty cycle (%), type 50.00.
  31. Leave all other options at their default values.
  32. Click Finish. Page 18 appears.
  33. On page 18, ensure that the Text Design File (.tdf), Pin Planner File (.ppf), AHDL Include file (.inc), Block Symbol File (.bsf), and Sample waveforms in summary file (.html and .jpg) are turned on.
  34. Click Finish. The shift_pll module is built.
  35. In the Symbol dialog box, click OK.
  36. Move the pointer to place the shift_pll symbol between the input and output ports in the shift_clk.bdf. Click to place the symbol. You have now completed the design file.
  37. On the File menu, click Save Project to save the design.
The following figure shows the completed design file.
Figure 23. ALTPLL shift_pll Design Schematic


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