Visible to Intel only — GUID: hzs1491260291713
Ixiasoft
Visible to Intel only — GUID: hzs1491260291713
Ixiasoft
2.2.2. CvP Update Mode
CvP update mode is a reconfiguration scheme that allows a host device to deliver an updated bitstream to a target FPGA device after the device enters user mode. In this mode, the FPGA device initializes by loading the full configuration image from any supported configuration scheme to the FPGA or after CvP initialization. Prior CvP initialization is not a prerequisite for performing a CvP update.
In user mode, the PCIe* links are available for normal PCIe* applications. You can use the CvP PCIe* link to perform an FPGA core image update. To perform the FPGA core image update, you can create one or more FPGA core images in the Quartus® Prime Pro Edition software that have identical connections to the periphery image.
For Stratix® 10 designs that include the HPS, it is important to note that performing an FPGA core image update also causes the HPS to be reconfigured. The updated bitstream contains the FPGA core data as well as the First Stage Bootloader (FSBL) used by the HPS.