Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

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ID 683704
Date 10/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization and Update Mode in Stratix® 10 7. Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations and Restrictions
1.3.1. CvP Limitations and Restrictions x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe* Wake-Up Time Requirement
4.1.2. PCIe* Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization and Update Mode in Stratix® 10 x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Avalon® Streaming Stratix® 10 Hard IP for PCI Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems 6.1.5.2. Modifying MSEL/DIP switch on Stratix® 10 FPGA Development Kit 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe* Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting up the Base Revision 6.2.4. Setting up and Compile the Updated Revision 6.2.5. Converting the SOF file of the Updated Revision 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Stratix® 10
7. Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History

6.1.5.3. Programming CvP Images

In Active Serial configuration mode, you must program the periphery image (.periph.jic) into your AS configuration device and then download the core image (.core.rbf) using the PCIe Link. You can use Active Serial x4 (Fast mode) to load .periph.jic into your selected CvP initialization enabled Stratix® 10 device.

After loading the periphery image, the Stratix® 10 is triggered to reconfigure from AS to load it. The link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities. Follow these steps to program and test the CvP functionality:

  1. Plug the Stratix® 10 FPGA Development Kit into the PCI Express slot of the DUT PC and power it ON. Intel recommends you use the ATX power supply included with the development kit.
  2. Open the Quartus® Prime Tools menu and select Programmer.
  3. Click Auto Detect to verify that the Intel® FPGA Download Cable recognizes the Stratix® 10 FPGA.
  4. Follow these steps to program the periphery image:
    1. Select Stratix 10 device, and then right click None under File column and select Change File.
    2. Navigate to .periph.jic file and click Open.
    3. Under Program/Configure column, select the respective devices. For example, 1SG280LU3S1 and EPCQL1024.
    4. Click Start to program the periphery image into EPCQL1024 flash.
    Figure 14. Illustrating the Specified Options to the Program Periphery Image
  5. After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the DUT PC to re-enumerate the link with the new image, power cycle the DUT PC and the Stratix® 10 FPGA Development Kit.
  6. You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
  7. Follow these steps to program the core image via PCIe link:
    1. Copy the .core.rbf file into /lib/firmware
    2. In the /lib/firmware directory, run the following command to use the FPGA manager to configure the core image.
      • Run: su to get root access.
      • Run: 
        echo <filename>.core.rbf > /sys/kernel/debug/fpga_manager/fpga0/firmware_name
  8. You can see your core image running on the Stratix® 10 FPGA Development Kit. Alternatively, print out the kernel message using the dmesg to ensure the CvP is completed successfully.
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