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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Stratix® 10
7. Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Intel Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
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2.1. Configuration Images
In CvP, you split your bitstream into two images: periphery image and core image.
You use the Quartus® Prime Pro Edition software to generate the images:
- Periphery image (*.periph.jic) — contains only CvP PCIe core. The entire periphery image is static and cannot be reconfigured. The size of the peripheral image varies across different Quartus® Prime versions but it will never exceed the recommended QSPI flash size for periphery image (256 Mb).
- Core image (*.core.rbf) — contains the entire device except the CvP PCIe core. The maximum size of the *.core.rbf file does not exceed the configuration bit stream size for the FPGA configuration stipulated in device datasheet.