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Ixiasoft
Visible to Intel only — GUID: vqz1488319349032
Ixiasoft
Recommended Timing Optimization and Analysis Assignments
Number | Done? | Checklist Item |
---|---|---|
1 | Turn on Optimize multi-corner timing on the Fitter Settings page in the Settings dialog box. | |
2 | Use create_clock and create_generated_clock to specify the frequencies and relationships for all clocks in your design. | |
3 | Use set_input_delay and set_output_delay to specify the external device or board timing parameters. | |
4 | Use derive_pll_clocks to create generated clocks for all PLL outputs, according to the settings in the PLL IP cores. Specify multicycle relationships for LVDS transmitters or receiver deserialization factors. | |
5 | Use derive_clock_uncertainty to automatically apply inter-clock, intra-clock, and I/O interface uncertainties. | |
6 | Use check_timing to generate a report on any problem with the design or applied constraints, including missing constraints. |
The assignments and settings described in this section are important for large designs such as those in Cyclone 10 GX devices.
When the Optimize multi-corner timing option is on, the design is optimized to meet its timing requirements at all timing process corners and operating conditions. Therefore, turning on this option helps create a design implementation that is more robust across PVT variations.
In your Timing Analyzer .sdc constraints file, apply the recommended constraints to your design.