Intel® Cyclone® 10 GX Device Design Guidelines

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ID 683703
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Design Guidelines
Intel® Cyclone® 10 GX Device Design Guidelines x
System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering PLLs and Clock Routing Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Quartus Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables Using the Parallel Flash Loader Intel® FPGA IP with MAX Devices
Configuration Features x
Data Compression Design Security Using Configuration Bitstream Encryption Remote System Upgrades SEU Mitigation and CRC Error Checks
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Quartus Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL and Transceiver Board Design Guidelines
Configuration Pin Connections x
DCLK and TCK Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
Board-Related Quartus Prime Settings x
Device-Wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Block I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable I/O Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Cyclone® 10 GX I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles Register Power-Up Levels and Control Signals Planning for Hierarchical and Team-Based Design
Reconfiguration x
Dynamic Reconfiguration
Planning for Hierarchical and Team-Based Design x
Planning Design Partitions Planning in Bottom-Up and Team-Based Flows Creating a Design Floorplan
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Quartus Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Formal Verification Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Quartus Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Quartus Prime Power Optimization Techniques x
Power Optimization Advisor
Appendix: Cyclone® 10 GX Transceiver Design Guidelines x
Transceiver PHY Architecture Overview Transceiver Bank Architecture PHY Layer Transceiver Components Transceiver Phase-Locked Loops Clock Generation Block (CGB) Calibration Transceiver Design Flow
PHY Layer Transceiver Components x
The GX Transceiver Channel
Transceiver Phase-Locked Loops x
Advanced Transmit (ATX) PLL Fractional PLL (fPLL) Channel PLL (CMU/CDR PLL)
Intel® Cyclone® 10 GX Device Design Guidelines

Quartus Prime Configuration Settings

This section covers several configuration options that you can set in the Intel® Quartus® Prime software before compilation to generate configuration or programming files. Your board and system design are affected by these settings and pins, so consider them in the planning stages. Set the options on the General category of the Device and Pin Options dialog box.

Optional Configuration Pins

You can enable the following optional configuration pins:

  • CLKUSR—The Enable user-supplied start-up clock (CLKUSR) option enables you to select which clock source is used for initialization, either the internal oscillator or an external clock provided on the CLKUSR pin. CLKUSR also allow you to drive the AS configuration clock (DCLK) at 100 MHz maximum. You can enable this feature in the Configuration page of the Device and Pins Option dialog box. The CLKUSR pin is also used as the clock for transceiver calibration, and is a mandatory requirement when using transceivers.
  • INIT_DONE—To check if the device has completed initialization and is in user mode, you can monitor the INIT_DONE pin. Enable the INIT_DONE pin with the Enable INIT_DONE output option. During the reset stage, after the device exits POR, and during the beginning of configuration, the INIT_DONE pin is tri-stated and pulled high due to an external pull-up resistor. The INIT_DONE pin is an open-drain output and requires an external pull-up to VCCPGM.
    Table 14.  Optional Configuration Pins Checklist
    Number Done? Checklist Item
    1   Plan the board design to support optional configuration pins CLKUSR and INIT_DONE, as required.

    Restart the Configuration After an Error

You can enable the Auto-restart after configuration error option so that when a configuration error occurs, the device drives nSTATUS low, which resets the device internally. The device releases its nSTATUS pin after a reset time-out period. This enables you to re-initiate the configuration cycle. The nSTATUS pin requires an external 10 kΩ pull-up resistor to VCCPGM.

Table 15.  Restart the Configuration After an Error Checklist
Number Done? Checklist Item
1   Plan board design to use the Auto-restart after configuration error option.
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