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System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Design Checklist
Appendix: Cyclone® 10 GX Transceiver Design Guidelines
Conclusion
Document Revision History
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Planning Guidelines for Debugging Tools
Number | Done? | Checklist Item |
---|---|---|
1 | Select on-chip debugging scheme(s) early to plan memory and logic requirements, I/O pin connections, and board connections. | |
2 | If you want to use Signal Probe incremental routing, the Signal Tap Embedded Logic Analyzer, Logic Analyzer Interface, In-System Memory Content Editor, In-System Sources and Probes, or Virtual JTAG IP core, plan your system and board with JTAG connections that are available for debugging. | |
3 | Plan for the small amount of additional logic resources used to implement the JTAG hub logic for JTAG debugging features. | |
4 | For debugging with the Signal Tap Embedded Logic Analyzer, reserve device memory resources to capture data during system operation. | |
5 | Reserve I/O pins for debugging with Signal Probe or the Logic Analyzer Interface so you do not have to change the design or board to accommodate debugging signals later. | |
6 | Ensure the board supports a debugging mode where debugging signals do not affect system operation. | |
7 | Incorporate a pin header or mictor connector as required for an external logic analyzer or mixed signal oscilloscope. | |
8 | To use debug tools incrementally and reduce compilation time, ensure incremental compilation is on so you do not have to recompile the design to modify the debug tool. | |
9 | To use the Virtual JTAG IP core for custom debugging applications, instantiate it in the HDL code as part of the design process. | |
10 | To use the In-System Sources and Probes feature, instantiate the IP core in the HDL code. | |
11 | To use the In-System Memory Content Editor for RAM or ROM blocks or the LPM_CONSTANT IP core, turn on the Allow In-System Memory Content Editor to capture and update content independently of the system clock option for the memory block in the IP catalog. |
If you intend to use any of the on-chip debugging tools, plan for the tool(s) when developing the system board, Intel® Quartus® Prime project, and design.