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System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Design Checklist
Appendix: Cyclone® 10 GX Transceiver Design Guidelines
Conclusion
Document Revision History
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Memory Power Reduction
Reduce the number of memory clocking events to reduce memory power consumption. You can use clock gating described in “Clock Power Management” or the clock enable signals in the memory ports.
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