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System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Design Checklist
Appendix: Cyclone® 10 GX Transceiver Design Guidelines
Conclusion
Document Revision History
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Clock Feedback Mode
The default clock feedback mode is direct compensation mode.
Fractional PLLs support the following clock feedback modes:
- Direct compensation
- Feedback compensation bonding
I/O PLLs support the following clock feedback modes:
- Direct compensation
- Normal compensation
- Source synchronous compensation
- LVDS compensation
- ZDB compensation
- External feedback compensation
Table 46. Clock Feedback Mode Checklist Number Done? Checklist Item 1 Ensure you select the correct PLL feedback compensation mode.