Intel® Stratix® 10 Logic Array Blocks and Adaptive Logic Modules User Guide

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ID 683699
Date 3/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 LAB and ALM Overview 2. Intel® Hyperflex™ Register 3. Intel® Stratix® 10 LAB and ALM Architecture and Features 4. Document Revision History for the Intel® Stratix® 10 LAB and ALM User Guide
3. Intel® Stratix® 10 LAB and ALM Architecture and Features x
3.1. LAB 3.2. ALM
3.1. LAB x
3.1.1. MLAB 3.1.2. Local and Direct Link Interconnects 3.1.3. Carry Chain Interconnects 3.1.4. LAB Control Signals
3.1.4. LAB Control Signals x
3.1.4.1. Clear Logic Control
3.2. ALM x
3.2.1. ALM Resources 3.2.2. ALM Output 3.2.3. ALM Operating Modes
3.2.3. ALM Operating Modes x
3.2.3.1. Normal Mode 3.2.3.2. Extended LUT Mode 3.2.3.3. Arithmetic Mode
3.2.3.3. Arithmetic Mode x
3.2.3.3.1. Carry Chain
1. Intel® Stratix® 10 LAB and ALM Overview
2. Intel® Hyperflex™ Register
3. Intel® Stratix® 10 LAB and ALM Architecture and Features
4. Document Revision History for the Intel® Stratix® 10 LAB and ALM User Guide

3.1.2. Local and Direct Link Interconnects

Each LAB can drive out 40 ALM outputs. Two groups of 20 ALM outputs can drive the adjacent LABs directly through direct-link interconnects.

The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility.

The local interconnect drives the ALM inputs. ALM outputs, as well as column and row interconnects drive the local interconnect. Neighboring LABs, MLABs, M20K blocks, or digital signal processing (DSP) blocks from the left or right can also drive the LAB's local interconnect using the direct link connection.

Figure 3.  Intel® Stratix® 10 LAB Local and Direct Link Interconnects
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