Early Power Estimator for Intel® Arria® 10 FPGAs User Guide

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ID 683688
Date 9/27/2022
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Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Arria® 10 2. Setting Up the Early Power Estimator for Intel® Arria® 10 3. Early Power Estimator for Intel® Arria® 10 Graphical User Interface 4. Early Power Estimator Worksheets for Intel® Arria® 10 5. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Arria® 10 6. Document Revision History for Early Power Estimator for Intel Arria® 10 FPGAs User Guide A. Measuring Static Power
1. Overview of the Early Power Estimator for Intel® Arria® 10 x
1.1. Power Model Status
2. Setting Up the Early Power Estimator for Intel® Arria® 10 x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
3. Early Power Estimator for Intel® Arria® 10 Graphical User Interface x
3.1. Early Power Estimator Input Fields 3.2. Early Power Estimator Output Fields 3.3. Early Power Estimator Input/Output Fields 3.4. Early Power Estimator Field Shading 3.5. Early Power Estimator Input Field Dependencies 3.6. Early Power Estimator Buttons
4. Early Power Estimator Worksheets for Intel® Arria® 10 x
4.1. Arria® 10 EPE - Common Worksheet Elements 4.2. Arria® 10 EPE - Main Worksheet 4.3. Arria® 10 EPE - Logic Worksheet 4.4. Arria® 10 EPE - RAM Worksheet 4.5. Arria® 10 EPE - DSP Worksheet 4.6. Arria® 10 EPE - Clock Worksheet 4.7. Arria® 10 EPE - PLL Worksheet 4.8. Arria® 10 EPE - I/O Worksheet 4.9. Arria® 10 EPE - I/O-IP Worksheet 4.10. Arria® 10 EPE - XCVR Worksheet 4.11. Arria® 10 EPE - HPS Worksheet 4.12. Arria® 10 EPE - Report Worksheet 4.13. Arria® 10 EPE - Enpirion Worksheet
5. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Arria® 10 x
5.1. Toggle Rate 5.2. Airflow 5.3. Temperature 5.4. Heat Sink
1. Overview of the Early Power Estimator for Intel® Arria® 10
2. Setting Up the Early Power Estimator for Intel® Arria® 10
3. Early Power Estimator for Intel® Arria® 10 Graphical User Interface
4. Early Power Estimator Worksheets for Intel® Arria® 10
5. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Arria® 10
6. Document Revision History for Early Power Estimator for Intel Arria® 10 FPGAs User Guide
A. Measuring Static Power

4.9. Arria® 10 EPE - I/O-IP Worksheet

Each row in the I/O-IP worksheet of the Early Power Estimator (EPE) for Arria® 10 represents a design module. You use the I/O-IP worksheet to instantiate external memory interface and HPS IPs supported in Arria® 10 . The I/O-IP worksheet populates other EPE worksheets with resources used by a selected IP.

Analog I/O power and digital power of hard memory controllers and HPS IPs entered on this tab are reported in the Analog Power and Digital Power fields of the I/O worksheet. If the IP uses other resource types (for example Logic or PLL), the power is reported on the corresponding worksheet.

Figure 21. I/O-IP Worksheet of the Early Power Estimator


I/O-IP Worksheet Information

Column Heading Description
Module Specify a name for the IP in this column. The module name depends on the selected IP type. It helps to cross-reference each IP module and its corresponding auto-populated entries on other worksheets.
IP Specifies the name of the IP in the design.
Voltage Specifies the I/O voltage of the signaling between periphery device and interface.
Data Width (Bits) Specifies the interface data width of the specific IP (in bits).
Data Group Width Specifies the number of DQ pins per data group.
Memory Device(s) Specifies the number of memory devices connected to the interface.
Address Width Specifies the address width. This value is used to derive the total number of address pins required.
DDR Rate Specifies the clock rate of user logic. Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200MHz.
PHY Rate Specifies the clock rate of PHY logic. Determines the clock frequency of PHY logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800MHz, a "Quarter rate" interface means that the PHY logic in the FPGA runs at 200MHz.
Memory Clock Freq (MHz) Specifies the frequency of memory clock (in MHz).
PLL Reference Clock Freq (MHz) Specifies the PLL Reference Clock Frequency (in MHz).
User Comments Enter any comments. This is an optional entry.
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