eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 6/21/2024
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Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interface Overview 6. eCPRI IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. About the eCPRI IP x
1.1. eCPRI Intel® FPGA IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. eCPRI IP Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interface Overview
6. eCPRI IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

5.1. eCPRI IP Clock Signals

Table 29.  eCPRI IP Input Clocks
Signal Name Width (Bits) I/O Direction Description
clk_tx 1 Input eCPRI IP TX clock.

For 25G eCPRI data rate variations, the default frequency value is 390.625 MHz.

For 10G eCPRI data rate variations, the default frequency value is 156.25 MHz.
clk_rx 1 Input eCPRI IP RX clock.

For 25G eCPRI data rate variations, the default frequency value is 390.625 MHz.

For 10G eCPRI data rate variations, the default frequency value is 156.25 MHz.
mac_clk_tx 1 Input Ethernet MAC TX clock.
The frequency of mac_clk_tx depends on device and data rate:
Device Data Rate mac_clk_tx Frequency (MHz)
Agilex™ 7 (E-tile) 25G 402.835
10G 161.32
Agilex™ 7 (F-tile) 25G 402.835
10G

402 or 415

1
Stratix® 10 (H-tile) 25G 390.625
10G 156.25
Stratix® 10 (E-tile) 25G 402.835
10G 161.32
Arria® 10 10G 156.25
mac_clk_rx 1 Input Ethernet MAC RX clock.
  • For the Stratix® 10 H-tile IP variations, the default frequency value is 390.625 MHz.
  • For the Stratix® 10 E-tile IP variations, the default frequency value is 402.835 MHz.
  • For the Agilex™ 7 E-tile and F-tile IP variations, the default frequency value is 402.835 MHz.
clk_csr 1 Input CSR clock. The default frequency value can be 100 MHz to 162 MHz.
ext_sink_clk 1 Input External user interface clock. The user needs to drive this clock at the same clock frequency configured at clk_tx.
cpri_clkout[N] 1 Input Master clock for the CPRI IP core.
The frequency of cpri_clkout[N] depends on the CPRI line bit rate:
CPRI Line Bit Rate cpri_clkout[N] Frequency
0.6144 Gbps 15.36 MHz
1.2288 Gbps 30.72 MHz
2.4576 Gbps 61.44 MHz
3.0720 Gbps 76.80 MHz
4.9152 Gbps 122.88 MHz
6.1440 Gbps 153.6 MHz
8.11008 Gbps 245.76 MHz
9.8304 Gbps 245.76 MHz
10.1376 Gbps 153.60 MHz2
307.20 MHz3
12.16512 Gbps 184.32 MHz
24.33024 Gbps 368.64 MHz
iwf_gmii_rxclk[N] 1 Input iwf_gmii_txclk clocks the GMII transmitter interface and iwf_gmii_rxclk clocks the GMII receiver interface. You must drive these clocks at the frequency of 125 MHz to achieve the 1000 Mbps bandwidth required for this interface.

These clocks are present only if you set the value of Ethernet PCS interface to the value of GMII in the CPRI parameter editor.

iwf_gmii_txclk[N] 1 Input
gmii_rxclk[N] 1 Output gmii_txclk clocks the GMII transmitter interface and gmii_rxclk clocks the GMII receiver interface. You must drive these clocks at the frequency of 125 MHz to achieve the 1000 Mbps bandwidth required for this interface.

These clocks are present only if you set the value of Ethernet PCS interface to the value of GMII in the CPRI parameter editor.

gmii_txclk[N] 1 Output
Related Information
1 Refer to Clock Connections in PTP-Based Synchronous and Asynchronous Operation and System PLL Clock in Clocks in F-Tile​ Ethernet Intel FPGA Hard IP User Guide.
2 For Agilex™ 7 E-tile and F-tile and Stratix® 10 E-tile device variations.
3 For all other device variations.
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