eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 11/15/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

5.7.3. 10G Ethernet MAC 1588 PTP Signals

Table 35.  Signals of the 10G Ethernet MAC 1588 PTP All signals are synchronous to clk_tx clock.
Signal Name Width Direction Description
ptp_timestamp_insert 1 Output

Indicates the current packet on the TX client interface is a 1588 PTP packet and directs the IP core to process the packet in one-step processing insertion mode. In this mode, the IP core overwrites the timestamp of the packet with the timestamp when the packet appears on the TX Ethernet link.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet.

ptp_tx_etstamp_ins_ctrl_residence_time_update 1 Output

Indicates the current packet on the TX client interface is a 1588 PTP packet and directs the IP core to process the packet in one-step processing correction mode. In this mode, the IP core adds the latency through the IP core (residence time) to the current contents of the timestamp field.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet.

tx_etstamp_ins_ctrl_times tamp_format 1 Output

Specifies the timestamp format (V1 or V2 format) for the current packet if the TX client simultaneously asserts tx_etstamp_ins_ctrl_timestamp_insert.

Valid value is:
  • Tie to 0 to indicate 96-bit timestamp format (V2).

The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

tx_etstamp_ins_ctrl_residence_time_calc_format 1 Output

Specifies the TOD format (Intel 64-bit TOD format or the V2 96-bit format) for the current packet if the TX client simultaneously asserts tx_etstamp_ins_ctrl_residence_time_update.

Value is:
  • Tie to 0 to indicate 96-bit TOD format (V2)

The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

ptp_offset_timestamp 16 Output

Specifies the byte offset of the timestamp information in the current packet if the TX client simultaneously asserts tx_etstamp_ins_ctrl_timestamp_insert.

The IP core overwrites the value at this offset.

The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

The timestamp has 96 bits. In this case, the IP core inserts ten bytes (bits [95:16]) of the timestamp at this offset and the remaining two bytes (bits [15:0]) of the timestamp at the offset specified in tx_etstamp_ins_ctrl_offset_correction_field.

ptp_offset_correction_field 16 Output

If the TX client simultaneously asserts tx_etstamp_ins_ctrl_residence_time_update, this signal specifies the byte offset of the correction field in the current packet.

If the TX client simultaneously asserts tx_etstamp_ins_ctrl_timestamp_insert and deasserts (sets to the value of 0) the tx_etstamp_ins_ctrl_timestamp_format signal, this signal specifies the byte offset of bits [15:0]] of the timestamp.

The TX client must maintain the desired value on this signal while the TX SOP signal is asserted.

tx_etstamp_ins_ctrl_checksum_zero 1 Output

The TX client asserts this signal during a TX SOP cycle to tell the IP core to zero the UDP checksum in the current packet.

A zeroed UDP checksum indicates the checksum value is not necessarily correct. This information is useful to tell the application to skip checksum checking of UDP IPv4 packets. This function is illegal for UDP IPv6 packets.

tx_etstamp_ins_ctrl_offset_checksum_field 16 Output

Indicates the byte offset of the UDP checksum in the current packet.

The TX client must ensure this signal has a valid value during each TX SOP cycle when it also asserts the tx_etstamp_ins_ctrl_checksum_zero signal.

Holds the byte offset of the two bytes in the packet that the IP core should reset.

tx_etstamp_ins_ctrl_checksum_correct 1 Output

The TX client asserts this signal during a TX SOP cycle to tell the IP core to update (correct) the UDP checksum in the current packet.

This signal is asserted for correct processing of UDP IPv6 packets.

tx_etstamp_ins_ctrl_offset_checksum_correction 16 Output

Indicates the byte offset of the UDP checksum in the current packet.

The TX client must ensure this signal has a valid value during each TX SOP cycle when it also asserts the tx_etstamp_ins_ctrl_checksum_correct signal.

Holds the byte offset of the two bytes in the packet that the IP core should correct. This signal is meaningful only in one-step clock mode.

tx_path_delay_10g_data Output 16 or 24 Connect this to the Intel FPGA PHY IP. This bus carries the path delay, which is measured between the physical network and the PHY side of the MAC IP Core (XGMII). The MAC IP core uses this value while generating the egress timestamp to account for the delay. The path delay is in the following format:
  • Bit [9:0]: Fractional number of clock cycle
  • Bits [23/15:10]: Number of clock cycle
tx_egress_p2p_update Output 1

Assert this signal when the correction factor is added with <meanPathDelay> given by tx_egress_p2p_val for a transmit frame, as part of peer-to-peer mechanism.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket).

tx_egress_p2p_val Output 46 This represents <meanPathDelay> for peer to peer operations.
  • Bits [45:16]: Link delay in nanoseconds field
  • Bits [15:0]: Link delay in fractional nanoseconds field
ptp_timestamp_request_valid 1 Output

Indicates the current packet on the TX client interface is a 1588 PTP packet and directs the IP core to process the packet in two-step processing mode.

In this mode, the IP core outputs the timestamp of the packet when it exits the IP core, and does not modify the packet timestamp information.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet.

ptp_timestamp_request_fingerprint 8 Output

Fingerprint of the current packet.

The TX client must assert and deassert this signal synchronously with the TX SOP signal for the 1588 PTP packet and eCPRI one way delay measurement packet.

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