eCPRI Intel® FPGA IP User Guide

ID 683685
Date 8/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.5. Interrupt

Table 28.  Interrupt SignalsThis signal is synchronous to clk_csr signal.
Signal Name Width (Bits) I/O Direction Description
err_interrupt 1 Output Error interrupt signal. Indicates errors occur in the eCPRI IP. Software can poll eCPRI error message register to determine the error info.