eCPRI Intel® FPGA IP User Guide

ID 683685
Date 7/01/2022
Public

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5.4. RX Time of Day Interface

Table 27.  Signals of the RX Time of Day InterfaceAll signals are synchronous to clk_rx clock.
Signal Name Width (Bits) I/O Direction Description
rx_tod_time_of_day_96b_data 96 Input Current V2-format (96-bit) TOD in clk_rxmac clock domain.
rx_ingress_timestamp_96b_data 96 Input Whether or not the current packet on the RX client interface is a 1588 PTP packet, indicates the V2-format timestamp when the IP core received the packet on the Ethernet link. The IP core provides a valid value on this signal in the same cycle it asserts the RX SOP signal for 1588 PTP packets.
rx_ingress_timestamp_96b_valid 1 Input Indicates that the rx_ingress_timestamp_96b_data signal is valid in the current cycle. This signal is redundant with the RX SOP signal for 1588 PTP packets.
ext_rx_ingress_timestamp_96b_data 96 Output Indicates V2-format timestamp when the IP core receives the RX packet on the Ethernet link. The IP core provides a valid value on this signal in the same cycle it asserts the RX SOP signal for 1588 PTP packets.