eCPRI Intel® FPGA IP User Guide

ID 683685
Date 12/14/2021
Public

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2.4. Simulating the IP Core

You can simulate your eCPRI IP variation using any of the vendor-specific IEEE encrypted functional simulation models which are available in the <instance_name>/sim subdirectory of your project directory.

The eCPRI IP core supports the Synopsys* VCS* , Synopsys* VCS* MX, Siemens* EDA ModelSim* SE, Aldec* Riviera-PRO* and Xcelium* Parallel simulators. The eCPRI IP core generates a Verilog HDL and VHDL simulation model. The IP core parameter editor offers you the option of generating a Verilog HDL or VHDL simulation model for the IP core. The IP core design example also supports Verilog HDL/VHDL simulation model or testbench.
Note: In the Intel® Quartus® Prime Pro Edition software version 21.2, the eCPRI IP core only supports Synopsys VCS*simulator for Intel® Agilex™ F-tile designs.

For more information about functional simulation models for Intel FPGA IP cores, refer to the Simulating Intel FPGA Designs chapter in Quartus Prime Pro Edition User Guide: Third-party Simulation.