Nios II Flash Accelerator Using Max10

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ID 683684
Date 6/30/2015
Public
Document Table of Contents
Document Table of Contents x
1. Nios II Flash Accelerator Using Max10
1. Nios II Flash Accelerator Using Max10 x
1.1. Introduction 1.2. Feature Description 1.3. Parameter 1.4. Performance 1.5. Document Revision History
1.2. Feature Description x
1.2.1. Cache Operation Block 1.2.2. Pre-fetch Block 1.2.3. Address Generator Block 1.2.4. Cache (Registers) Block 1.2.5. Interfaces
1. Nios II Flash Accelerator Using Max10

1.2.5. Interfaces

It is a 32-bit read-only Avalon-MM master interface. It has support for wrapping burst where the burst starts from the critical word first. The burst size is configurable through the line size parameter where the burst count size equals to Line Size divided by 32-bits data.

Note: The Max 10 on-chip flash IP “Read burst mode” parameter needs to be configured to wrapping burst.
Level Two Title