Intel Agilex® 7 Configuration User Guide

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Date 2/05/2024
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 Configuration User Guide 2. Intel Agilex® 7 Configuration Details 3. Intel Agilex® 7 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel Agilex® 7 Configuration Features 7. Intel Agilex® 7 Debugging Guide 8. Intel Agilex® 7 Configuration User Guide Archives 9. Document Revision History for the Intel Agilex® 7 Configuration User Guide
1. Intel Agilex® 7 Configuration User Guide x
1.1. Intel Agilex® 7 Configuration Overview 1.2. Intel Agilex® 7 Configuration Architecture
1.1. Intel Agilex® 7 Configuration Overview x
1.1.1. Configuration and Related Signals 1.1.2. Intel Download Cables Supporting Configuration in Intel Agilex® 7 Devices
1.2. Intel Agilex® 7 Configuration Architecture x
1.2.1. Secure Device Manager
1.2.1. Secure Device Manager x
1.2.1.1. Updating the SDM Firmware 1.2.1.2. Specifying Boot Order for Intel Agilex® 7 SoC Devices
2. Intel Agilex® 7 Configuration Details x
2.1. Intel Agilex® 7 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and Transceivers 2.5. Intel Agilex® 7 Configuration Pins 2.6. Configuration Clocks 2.7. Intel Agilex® 7 Configuration Time Estimation 2.8. Generating Compressed .sof File
2.5. Intel Agilex® 7 Configuration Pins x
2.5.1. SDM Pin Mapping 2.5.2. MSEL Settings 2.5.3. Device Configuration Pins for Optional Configuration Signals
2.5.3. Device Configuration Pins for Optional Configuration Signals x
2.5.3.1. Specifying Optional Configuration Pins 2.5.3.2. Enabling Dual-Purpose Pins 2.5.3.3. I/O Standards and Features for Configuration Pins 2.5.3.4. SDM I/O Pins for Power Management and SmartVID 2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)
2.5.3.1. Specifying Optional Configuration Pins x
2.5.3.1.1. nCONFIG 2.5.3.1.2. nSTATUS 2.5.3.1.3. CONF_DONE and INIT_DONE 2.5.3.1.4. SDM_IO Pins
2.5.3.3. I/O Standards and Features for Configuration Pins x
2.5.3.3.1. IBIS Model
2.6. Configuration Clocks x
2.6.1. Setting Configuration Clock Source 2.6.2. OSC_CLK_1 Clock Input
3. Intel Agilex® 7 Configuration Schemes x
3.1. Avalon-ST Configuration 3.2. AS Configuration 3.3. JTAG Configuration
3.1. Avalon-ST Configuration x
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II) x
3.1.7.1. Functional Description 3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration 3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP 3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP 3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP 3.1.7.6. Supported Flash Memory Devices
3.1.7.1. Functional Description x
3.1.7.1.1. Generating and Programming a .pof into CFI Flash 3.1.7.1.2. Implementing Multiple Pages in the Flash .pof 3.1.7.1.3. Storing Option Bits 3.1.7.1.4. Verifying the Option Bit Start and End Addresses 3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration x
3.1.7.2.1. Parallel Flash Loader II Intel® FPGA IP Parameters 3.1.7.2.2. Parallel Flash Loader II Intel® FPGA IP Signals
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP 3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address 3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration 3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins 3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash 3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash 3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins 3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.5.1. Converting .sof to .pof File 3.1.7.5.2. Programming CPLDs and Flash Memory Devices Sequentially 3.1.7.5.3. Programming CPLDs and Flash Memory Devices Separately 3.1.7.5.4. Defining New CFI Flash Memory Device
3.2. AS Configuration x
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
3.2.5. Skew Tolerance Guidelines x
3.2.5.1. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.5.2. Maximum Allowable External nCSO Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices x
3.2.6.1. Programming Serial Flash Devices using the AS Interface 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface
3.2.7. Serial Flash Memory Layout x
3.2.7.1. Understanding Quad SPI Flash Byte-Addressing
3.2.10. Intel® Quartus® Prime Programming Steps x
3.2.10.1. Generating Programming Files using the Programming File Generator 3.2.10.2. Programming .pof files into Serial Flash Device 3.2.10.3. Programming .jic files into Serial Flash Device
3.3. JTAG Configuration x
3.3.1. JTAG Configuration Scheme Hardware Components and File Types 3.3.2. JTAG Device Configuration 3.3.3. JTAG Multi-Device Configuration 3.3.4. Debugging Guidelines for the JTAG Configuration Scheme
3.3.2. JTAG Device Configuration x
3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections 3.3.2.2. JTAG Single-Device Configuration using a Microprocessor
3.3.3. JTAG Multi-Device Configuration x
3.3.3.1. JTAG Multi-Device Configuration using Download Cable
4. Including the Reset Release Intel® FPGA IP in Your Design x
4.1. Understanding the Reset Release IP Requirement 4.2. Instantiating the Reset Release IP In Your Design 4.3. Gating the PLL Reset Signal 4.4. Guidance When Using Partial Reconfiguration (PR) 4.5. Detailed Description of Device Configuration
4.5. Detailed Description of Device Configuration x
4.5.1. Device Initialization 4.5.2. Embedded Memory Block Initial Conditions 4.5.3. Protecting State Machine Logic
5. Remote System Update (RSU) x
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example 5.7. Debugging Guidelines for RSU Configuration
5.1. Remote System Update Functional Description x
5.1.1. RSU Glossary 5.1.2. Remote System Update Using AS Configuration 5.1.3. Remote System Update Configuration Images 5.1.4. Remote System Update Configuration Sequence 5.1.5. RSU Recovery from Corrupted Images 5.1.6. Updates with the Factory Update Image
5.3. Commands and Responses x
5.3.1. Operation Commands Resetting Quad SPI Flash RSU SDM Command Use Case 5.3.2. Error Code Responses 5.3.3. Error Code Recovery
5.4. Quad SPI Flash Layout x
5.4.1. High Level Flash Layout 5.4.2. Detailed Quad SPI Flash Layout
5.4.1. High Level Flash Layout x
5.4.1.1. Standard (non-RSU) Image Layout in Flash 5.4.1.2. RSU Image Layout in Flash – SDM Perspective 5.4.1.3. RSU Image Layout – Your Perspective
5.4.1.2. RSU Image Layout in Flash – SDM Perspective x
5.4.1.2.1. Firmware Version Information
5.4.2. Detailed Quad SPI Flash Layout x
5.4.2.1. RSU Image Sub-Partitions Layout 5.4.2.2. Sub-Partition Table Layout 5.4.2.3. Configuration Pointer Block Layout 5.4.2.4. Modifying the List of Application Images
5.5. Generating Remote System Update Image Files Using the Programming File Generator x
5.5.1. Generating the Initial RSU Image 5.5.2. Generating an Application Image 5.5.3. Generating a Factory Update Image 5.5.4. Command Sequence To Perform Quad SPI Operations
5.5.1. Generating the Initial RSU Image x
5.5.1.1. Generating the Initial RSU Image Using SOF Files 5.5.1.2. Generating the Initial RSU Image Using RBF Files
5.6. Remote System Update from FPGA Core Example x
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
6. Intel Agilex® 7 Configuration Features x
6.1. Device Security 6.2. Configuration via Protocol 6.3. Partial Reconfiguration
7. Intel Agilex® 7 Debugging Guide x
7.1. Configuration Debugging Checklist 7.2. Intel Agilex® 7 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. E-Tile Transceivers May Fail To Configure 7.8. Understanding and Troubleshooting Configuration Pin Behavior 7.9. Configuration Debugger Tool
1. Intel Agilex® 7 Configuration User Guide
2. Intel Agilex® 7 Configuration Details
3. Intel Agilex® 7 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel Agilex® 7 Configuration Features
7. Intel Agilex® 7 Debugging Guide
8. Intel Agilex® 7 Configuration User Guide Archives
9. Document Revision History for the Intel Agilex® 7 Configuration User Guide

5.3.1. Operation Commands

Resetting Quad SPI Flash

Important: For Intel Agilex® 7 devices, you must connect the serial flash or quad SPI flash reset pin to the AS_nRST pin. The SDM must fully control the QSPI reset. Do not connect the quad SPI reset pin to any external host.

RSU SDM Command Use Case

Important: All RSU-related SDM commands (RSU_IMAGE_UPDATE, RSU_GET_SPT, RSU_STATUS, and RSU_NOTIFY) are only valid when the SDM loads the RSU image from QSPI flash using AS x4 configuration mode.
Table 45.  Command List and Description
Command Code (Hex) Command Length 14 Response Length 14 Description
RSU_IMAGE_UPDATE 5C 2 0

Triggers reconfiguration from the data source that can be either the factory or an application image.

This command takes an optional 64-bit argument that specifies the reconfiguration data address in the flash. When sending the argument to the IP, you first send bits [31:0] followed by bits [63:32]. If you do not provide this argument its value is assumed to be 0.

  • Bit [31:0]: The start address of an application image.
  • Bit [63:32]: Reserved (write as 0).

Once the device processes this command, it returns the response header to response FIFO before it proceeds to reconfigure the device. Ensure the host PC or host controller stops servicing other interrupts and focuses on reading the response header data to indicate the command completed successfully. Otherwise, the host PC or host controller may not be able to receive the response once the reconfiguration process started.

Once the device proceeds with reconfiguration, the link between the external host and FPGA is lost. If you use PCIe in your design, you need to re-enumerate the PCIe link.

Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
RSU_GET_SPT 5A 0 4

RSU_GET_SPT retrieves the quad SPI flash location for the two sub-partition tables that the RSU uses: SPT0 and SPT1.

The 4-word response contains the following information:

Word Name Description
0 SPT0[63:32] SPT0 address in quad SPI flash.
1 SPT0[31:0]
2 SPT1[63:32] SPT1 address in quad SPI flash.
3 SPT1[31:0]
CONFIG_STATUS 4 0 6

Reports the status of the last reconfiguration. You can use this command to check the configuration status during and after configuration. The response contains the following information:

Word Summary Description
0 State Describes the most recent configuration related error. Returns 0 when there are no configuration errors.
The error field has 2 fields:
  • Upper 16 bits: Major error code.
  • Lower 16 bits: Minor error code.

Refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel® FPGA IP User Guide for more information.

1 Quartus Version
Available in Intel® Quartus® Prime software versions between 19.4 and 21.2, the field displays:
  • Bit [31:28]: Index of the firmware or decision firmware copy that was used the most recently. Possible values are 0, 1, 2, and 3.
  • Bit [27:24]: Reserved
  • Bit [23:16]: Value is '0'
Available in Intel® Quartus® Prime software version 21.3 or later, the Quartus version displays:
  • Bit [31:28]: Index of the firmware or decision firmware copy that was used the most recently. Possible values are 0, 1, 2, and 3.
  • Bit [27:24]: Reserved
  • Bit [23:16]: Major Quartus release number
  • Bit [15:8]: Minor Quartus release number
  • Bit [7:0]: Quartus update number
For example, in Intel® Quartus® Prime software version 21.3.1, the following values represent the major and minor Quartus release numbers, and the Quartus update number:
  • Bit [23:16] = 8'd21 = 8'h15
  • Bit [15:8] = 8'd3 = 8'h3
  • Bit [7:0] = 8'd1 = 8'h1
2 Pin status
  • Bit [31]: Current nSTATUS output value (active low)
  • Bit [30]: Detected nCONFIG input value (active low)
  • Bit [29:8]: Reserved
  • Bit [7:6]: Configuration clock source
    • 01 = Internal oscillator
    • 10 = OSC_CLK_1
  • Bit [5:3]: Reserved
  • Bit [2:0]: The MSEL value at power up
3 Soft function status Contains the value of each of the soft functions, even if you have not assigned the function to an SDM pin.
  • Bit [31:6]: Reserved
  • Bit [5]: HPS_WARMRESET
  • Bit [4]: HPS_COLDRESET
  • Bit [3]: SEU_ERROR
  • Bit [2]: CVP_DONE
  • Bit [1]: INIT_DONE
  • Bit [0]: CONF_DONE
4 Error location Contains the error location. Returns 0 if there are no errors.
5 Error details Contains the error details. Returns 0 if there are no errors.
RSU_STATUS 5B 0 9 Reports the current remote system upgrade status. You can use this command to check the configuration status during configuration and after it has completed. This command returns the following responses:
Word Summary Description
0-1 Current image Flash offset of the currently running application image.
2-3 Failing image

Flash offset of the highest priority failing application image. If multiple images are available in flash memory, stores the value of the first image that failed. A value of all 0s indicates no failing images. If there are no failing images, the remainder of the remaining words of the status information do not store valid information.

Note: A rising edge on nCONFIG to reconfigure from AS x4, does not clear this field. Information about failing image only updates when the Mailbox Client Intel® FPGA IP receives a new RSU_IMAGE_UPDATE command and successfully configures from the update image.
4 State Failure code of the failing image.
The error field has two parts:
  • Bit [31:16]: Major error code
  • Bit [15:0]: Minor error code

Returns 0 for no failures. Refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel® FPGA IP User Guide for more information.

5 Version

RSU interface version and error source.

For more information, refer to RSU Status and Error Codes section in the Hard Processor System Remote System Update User Guide.

6 Error location Stores the error location of the failing image. Returns 0 for no errors.
7 Error details Stores the error details for the failing image. Returns 0 if there are no errors.
8 Current image retry counter

Count of the number of retries that have been attempted for the current image. The counter is 0 initially. The counter is set to 1 after the first retry, then 2 after a second retry.

Specify the maximum number of retries in your Intel® Quartus® Prime Settings File (.qsf). The command is: set_global_assignment -name RSU_MAX_RETRY_COUNT 3. Valid values for the MAX_RETRY counter are 1-3. The actual number of available retries is MAX_RETRY -1

This field was added in version 19.3 of the Intel® Quartus® Prime Pro Edition software.

RSU_NOTIFY 5D 1 0
Clears all error information in the RSU_STATUS response and resets the retry counter. The one-word argument has the following fields:
  • 0x00050000: Clear current reset retry counter. Resetting the current retry counter sets the counter back to zero, as if the current image was successfully loaded for the first time.
  • 0x00060000: Clear error status information.
  • All other values are reserved.

This command is not available before version 19.3 of the Intel® Quartus® Prime Pro Edition software.

QSPI_OPEN 32 0 0

Requests exclusive access to the quad SPI. You issue this request before any other QSPI requests. The SDM accepts the request if the quad SPI is not in use and the SDM is not configuring the device. Returns OK if the SDM grants access. Upon receiving the OK response, issue the QSPI_SET_CS command to select the flash devices.

The SDM grants exclusive access to the client using this mailbox. Other clients cannot access the quad SPI until the active client relinquishes access using the QSPI_CLOSE command.

Access to the QSPI flash memory devices using SDM_IO pins is only available for the AS x4 configuration scheme, JTAG configuration, and a design compiled for AS x4 configuration. For the Avalon® streaming interface ( Avalon® ST) configuration scheme, you must connect QSPI flash memories to GPIO pins.

Access to the quad SPI flash memory devices via any mailbox client IP is not available by default in designs that include the HPS, unless you disable the QSPI in HPS software configuration.

Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_CLOSE 33 0 0 Closes the exclusive access to the quad SPI interface.
Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_SET_CS 34 1 0 Specifies one of the attached quad SPI devices via the chip select lines. Takes a one-word argument as described below:
  • Bits[31:28]: Flash device to select. Below values correspond to the respective nCSO[3:0] pins.
    • Value 4'h0000 selects the flash that corresponds to nCSO[0].
    • Value 4'h0001 selects the flash that corresponds to nCSO[1].
    • Value 4'h0002 selects the flash that corresponds to nCSO[2].
    • Value 4'h0003 selects the flash that corresponds to nCSO[3].
  • Bits[27:0]: Reserved (write as 0).
Note: Intel Agilex® 7 devices support one AS x4 flash memory device for AS configuration from quad SPI device connected to nCSO[0]. Once the device enters user mode, you can then use up to four AS x4 flash memories with Mailbox Client Intel® FPGA IP or HPS as data storage. The Mailbox Client Intel® FPGA IP or HPS can use nCSO[3:0] to access quad SPI devices.

During AS x4 configuration scheme in Intel Agilex® 7 devices, this command is required after every QSPI_OPEN command.

During JTAG configuration scheme, this command is required after every QSPI_OPEN command.

Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_READ 3A 2 N

Reads the attached quad SPI device. The maximum transfer size is 4 kilobytes (KB) or 1024 words.

Takes two arguments:
  • The quad SPI flash address (one word). The address must be word aligned. The device returns the 0x1 error code for non-aligned addresses.
  • Number of words to read (one word).
When successful, returns OK followed by the read data from the quad SPI device. A failure response returns an error code.

For a partially successful read, QSPI_READ may erroneously return the OK status.

Note: You cannot run the QSPI_READ command while device configuration is in progress.
Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_WRITE 39 2+N 0

Writes data to the quad SPI device. The maximum transfer size is 4 kilobytes (KB) or 1024 words.

Takes three arguments:
  • The flash address offset (one word). The write address must be word aligned.
  • The number of words to write (one word).
  • The data to be written (one or more words).
A successful write returns the OK response code.

To prepare memory for writes, use the QSPI_ERASE command before issuing this command.

Note: You cannot run the QSPI_WRITE command while device configuration is in progress.
Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_ERASE 38 2 0 Erases a 4/32/64 KB sector of the quad SPI device. Takes two arguments:
  • The flash address offset to start the erase (one word). Depending on the number of words to erase, the start address must be:
    • 4 KB aligned if number words to erase is 0x400
    • 32 KB aligned if number words to erase is 0x2000
    • 64 KB aligned if number words to erase is 0x4000
    Returns an error for non-4/32/64 KB aligned addresses.
  • The number of words to erase is specified in multiples of:
    • 0x400 to erase 4 KB (100 words) of data. This option is the minimum erase size.
    • 0x2000 to erase 32 KB (500 words) of data
    • 0x4000 to erase 64 KB (1000 words) of data
A successful erase returns the OK response code.
Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_READ_DEVICE_REG 35 2 N Reads registers from the quad SPI device. The maximum read is 8 bytes. Takes two arguments:
  • The opcode for the read command.
  • The number of bytes to read.

A successful read returns the OK response code followed by the data read from the device. The read data return is in multiple of 4 bytes. If the bytes to read is not an exact multiple of 4 bytes, it is padded with multiple of 4 bytes until the next word boundary and the padded bit value is zero.

Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_WRITE_DEVICE_REG 36 2+N 0 Writes to registers of the quad SPI. The maximum write is 8 bytes. Takes three arguments:
  • The opcode for the write command.
  • The number of bytes to write.
  • The data to write.

To perform a sector erase or sub-sector erase, you must specify the serial flash address in most significant byte (MSB) to least significant byte (LSB) order as the following example illustrates.

To erase a sector of a Micron 2 gigabit (Gb) flash at address 0x04FF0000 using the QSPI_WRITE_DEVICE_REG command, write the flash address in MSB to LSB order as shown here:

Header: 0x00003036

Opcode: 0x000000DC

Number of bytes to write: 0x00000004

Flash address: 0x0000FF04

A successful write returns the OK response code. This command pads data that is not a multiple of 4 bytes to the next word boundary. The command pads the data with zero.

Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.
QSPI_SEND_DEVICE_OP 37 1 0 Sends a command opcode to the quad SPI. Takes one argument:
  • The opcode to send the quad SPI device.

A successful command returns the OK response code.

Important: When resetting quad SPI, you must follow instructions specified in Resetting Quad SPI Flash.

For CONFIG_STATUS and RSU_STATUS major and minor error code descriptions, refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel® FPGA IP User Guide .

Related Information
14 This number does not include the command or response header.
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