Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683672
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

1.5. Simulating the Design Example Testbench

Refer to Interlaken (2nd Generation) Hardware Design Example High Level Block for E-tile NRZ Mode Variations and Interlaken (2nd Generation) Hardware Design Example High Level Block for E-tile PAM4 Mode Variations block diagrams of the simulation testbench.
Figure 10. Procedure
Follow these steps to simulate the testbench:
  1. At the command prompt, change to the testbench simulation directory. The directory is <design_example_installation_dir>/example_design/testbench for Intel® Stratix® 10 devices.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete. Refer to the table Steps to Run Simulation.
    Table 4.  Steps to Run Simulation
    Simulator Instructions
    Questa*-Intel® FPGA Edition or QuestaSim* In the command line, type -do vlog_pro.do

    If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do vlog_pro.do

    VCS* In the command line, type sh vcstest.sh
    Xcelium* In the command line, type sh xcelium.sh
  3. Analyze the results. A successful simulation sends and receives packets, and displays "Test PASSED".
    The testbench for the design example completes the following tasks:
    • Instantiates the Interlaken (2nd Generation) Intel® FPGA IP.
    • Prints PHY status.
    • Checks metaframe synchronization (SYNC_LOCK) and word (block) boundaries (WORD_LOCK).
    • Waits for individual lanes to be locked and aligned.
    • Starts transmitting packets.
    • Checks packet statistics:
      • CRC24 errors
      • SOPs
      • EOPs
    The following sample output illustrates a successful simulation test run in Interlaken mode: 
    ******************************************
				INFO: Waiting for lanes to be aligned
	  				All of the receiver lanes are aligned and are ready to receive traffic.
***************************************************

***************************************************
				INFO: Start transmitting packets
***************************************************

***************************************************
				INFO: Stop transmitting packets
***************************************************

***************************************************
				INFO: Checking packets statistics
***************************************************

				CRC 24 errors reported: 0
				SOPs transmitted: 100
				EOPs transmitted: 100
				SOPs received: 100
				EOPs received: 100
				ECC error count: 0

***************************************************
				INFO: Test PASSED
***************************************************
    Note: The Interlaken design example simulation testbench sends 100 packets and receives 100 packets.
    The following sample output illustrates a successful simulation test run in Interlaken Look-aside mode: 
       Check TX and RX Counter equal or not
-------------------------------------------------
READ_MM: address 4000014 =  00000001

-------------------------------------------------
   De-assert Counter equal bit
-------------------------------------------------
WRITE_MM: address 4000001 gets 00000001
WRITE_MM: address 4000001 gets 00000000

-------------------------------------------------
   RX_SOP COUNTER
-------------------------------------------------
READ_MM: address 400000c =  0000006a

-------------------------------------------------
   RX_EOP COUNTER
READ_MM: address 400000d =  0000006a
-------------------------------------------------

READ_MM: address 4000010 =  00000000

-------------------------------------------------
   Display Final Report
-------------------------------------------------
     0 Detected Error
     0 CRC24 errors reported
   106 SOPs transmitted
   106 EOPs transmitted
   106 SOPs received
   106 EOPs received
-------------------------------------------------

-------------------------------------------------
   Finish Simulation
-------------------------------------------------

-------------------------------------------------
   TEST PASSED
--------------------------------------------------
    Note: The number of packets (SOPs and EOPs) varies per lane in Interlaken Look-aside design example simulation sample output.
Level Two Title