Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683672
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

1.6. Compiling and Configuring the Design Example in Hardware

Figure 11. Procedure
To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_installation_dir>/example_design/quartus/example_design.qpf>.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in your specified directory. Follow these steps to program the hardware example design on the Intel® Stratix® 10 device:
    1. Connect Development Kit to the host computer.
    2. Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example. Below is the frequency setting in the Clock Control application:
      • If you are targeting your design on Intel® Stratix® 10 GX Signal Integrity Development Kit with H-tile device:
        • Si5341 (U5), OUT5- Set to the value of pll_ref_clk 1 per your design requirement
      • If you are targeting your design on Intel® Stratix® 10 TX Signal Integrity Development Kit with H-tile device:
        • Si5341 (U3), OUT3- 50 MHz
        • Si5341 (U3), OUT9- Set to the value of pll_ref_clk 1 per your design requirement
      • If you are targeting your design on Intel® Stratix® 10 TX Signal Integrity Development Kit with E-tile:
        • Si5341 (U3), OUT3- 100 MHz
        • Si5341 (U3), OUT7- Set to the value of pll_ref_clk 1 per your design requirement (in NRZ mode)
        • Si5341 (U3), OUT4- Set to the value of pll_ref_clk 1 per your design requirement (in PAM4 mode)
        • Si5341 (U3), OUT2- Set to the value of mac_pll_ref_clk 1 per your design requirement (in PAM4 mode only)
    3. On the Tools menu, click Programmer.
    4. In the Programmer, click Hardware Setup.
    5. Select a programming device.
    6. Select and add the Intel® Stratix® 10 GX Signal Integrity Development Kit or Intel® Stratix® 10 TX Signal Integrity Development Kit to which your Intel® Quartus® Prime session can connect.
    7. Ensure that Mode is set to JTAG.
    8. Select the Intel® Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    9. In the row with your .sof, check the box for the .sof.
    10. Check the box in the Program/Configure column.
    11. Click Start.
Related Information
1 Not all frequencies can be derived by the Clock Control GUI application.
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