Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683672
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

2.2. Interface Signals

Table 5.  Design Example Interface Signals
Port Name Direction Width (Bits) Description
clk50 Input 1

System clock input. Clock frequency must be 50 MHz.

This pin refers to CLK_50M_S10 on the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit and CLK_BOT_PLL_100M_P on the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit .

mgmt_clk Input 1 System clock input. Clock frequency must be 100 MHz.

This signal is only available in Intel® Stratix® 10 E-tile device variations. This pin refers to CLK_BOT_PLL_100M_P on the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit.

pll_ref_clk / pll_ref_clk[1:0] 2 Input 1/2 Transceiver reference clock. Drives the RX CDR PLL.
Note: pll_ref_clk[1] is only available when you enable Preserve unused transceiver channels for PAM4 parameter in E-tile PAM4 mode IP variations.
rx_pin Input Number of lanes Receiver SERDES data pin.
tx_pin Output Number of lanes Transmit SERDES data pin.
rx_pin_n Input Number of lanes Receiver SERDES data pin.

This signal is only available in E-tile PAM4 mode device variations.

tx_pin_n Output Number of lanes Transmit SERDES data pin.

This signal is only available in E-tile PAM4 mode device variations.

mac_clk_pll_ref Input 1 This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk.

This signal is only available in E-tile PAM4 mode device variations.

usr_pb_reset_n Input 1 System reset.
Related Information
2 When you enable Preserve unused transceiver channels for PAM4 parameter, an additional reference clock port is added to preserve the unused PAM4 slave channel.
Level Two Title