Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683672
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

1.1. Hardware and Software Requirements

To test the example design, use the following hardware and software:
  • Intel® Quartus® Prime Pro Edition software
  • System Console
  • Supported simulators:
    • Siemens* EDA QuestaSim*
    • Synopsys* VCS*
    • Cadence* Xcelium*
    • Questa*-Intel® FPGA Edition
  • Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit (1SG280HU2F50E2VG) or Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit (1ST280EY2F55E2VG) for hardware testing
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