Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683672
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide

2.1. Design Example Behavior

To test the design in hardware, type the following commands in the System Console::
  1. Source the setup file: 
    % source  <design_example>uflex_ilk_0_example_design/example_design/hwtest/sysconsole_testbench.tcl
  2. Run the test: 
    % run_example_design
  3. The Interlaken (2nd Generation) hardware design example completes the following steps:
    1. Resets the Interlaken (2nd Generation) IP.
    2. Configures the Interlaken (2nd Generation) IP in internal loopback mode.
    3. Sends a stream of Interlaken packets with predefined data in the payload to the TX user data transfer interface of the IP core.
    4. Checks the received packets and reports the status. The packet checker included in the hardware design example provides the following basic packet checking capabilities:
    • Checks that the transmitted packet sequence is correct.
    • Checks that the received data matches the expected values by ensuring both the start of packet (SOP) and end of packet (EOP) counts align while data is being transmitted and received.
Level Two Title