5G LDPC-V Intel® FPGA IP User Guide

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ID 683670
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 5G LDPC-V Intel® FPGA IP 2. Getting Started with the Intel® FPGA IP 3. Designing with the 5G LDPC-V Intel® FPGA IP 4. 5G LDPC-V Intel® FPGA IP Functional Description 5. 5G LPDC-V IP User Guide Archive 6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide
1. About the 5G LDPC-V Intel® FPGA IP x
1.1. 5G LDPC-V Intel® FPGA IP Features 1.2. 5G LDPC-V Intel® FPGA IP Device Family Support 1.3. Release Information for the 5G LDPC-V Intel® FPGA IP 1.4. 5G LDPC-V Performance and Resources
2. Getting Started with the Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 5G LDPC-V IP Timeout Behavior
3. Designing with the 5G LDPC-V Intel® FPGA IP x
3.1. 5G LDPC-V IP Directory Structure 3.2. Generating a 5G LPDC-V IP 3.3. Simulating the 5G LDPC-V IP 3.4. 5G LDPC-V Simulation Results
3.2. Generating a 5G LPDC-V IP x
3.2.1. 5G LDPC-V IP Parameters
4. 5G LDPC-V Intel® FPGA IP Functional Description x
4.1. 5G LDPC-V Transmitter Functional Description 4.2. 5G LDPC-V Receiver Functional Description 4.3. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.4. 5G LDPC-V Throughput and Latency
4.1. 5G LDPC-V Transmitter Functional Description x
4.1.1. 5G LDPC-V Transmitter Signals 4.1.2. 5G LDPC-V Lifting Factor and Code Rate Indexes
4.2. 5G LDPC-V Receiver Functional Description x
4.2.1. 5G LDPC-V Receiver Signals
1. About the 5G LDPC-V Intel® FPGA IP
2. Getting Started with the Intel® FPGA IP
3. Designing with the 5G LDPC-V Intel® FPGA IP
4. 5G LDPC-V Intel® FPGA IP Functional Description
5. 5G LPDC-V IP User Guide Archive
6. Document Revision History for the 5G LDPC-V Intel® FPGA IP User Guide

1.4. 5G LDPC-V Performance and Resources

Intel derives the performance with Quartus® Prime Pro Edition v23.2

Dual decoders comprise LDPC1, LDPC2, derate matcher, HARQ and CRC. LDPC1 is a standard LDPC engine that processes all codewords. LDPC2 can increase throughput by processing smaller codewords up to Zmax.

Single decoders comprise LPDC, derate matcher, HARQ, and CRC, where the design achieves higher throughput (standard) or lower power (super lite).

Table 2.  Performance and Resources for Agilex™ 5 Devices
  • SM7 P4=SM7_PART_4S
  • AE5=A5EC065BB32AE5SR0
  • AE6=A5EC065BB32AE6SR0
All fMAX numbers are reduced by 15% for margins in your designs
Architecture Configuration Resource Utilization SM7 P4 AE5 AE6
ALM M20k DSP fMAX (MHz)
Encoder N/A 13.2k 27 2 390 323 305
Dual Decoder LDPC2 Zmax=192 100.4k 1,274 1 334 277 252
LDPC2 Zmax=192 using DSP 83.9k 1,274 631 332 273 255
Single Decoder Standard 74.8k 908 1 335 281 258
Standard using DSP 62.2k 908 487 329 278 254
Lite 54.6k 601 1 307 261 235
Super Lite 41.2k 554 1 307 261 235
Table 3.  Performance and Resources for Agilex™ 7 Devices
  • E1V=AGFB014R24B1E1V
  • E2V=AGFB014R24B2E2V
  • E3V=AGFB014R24B2E3V
  • E3E=AGFB014R24B2E3E
  • E4X=AGFB014R24B2E4X
  • E4F=AGFB014R24B2E4F
  • I1V=AGFB014R24B1I1V
  • I2V=AGFB014R24B2I2V
  • I3V=AGFB014R24B2I3V
  • I3E=AGFB014R24B2I3E
All fMAX numbers are reduced by 15% for margins in your designs
Architecture Configuration Resource Utilization E1V E2V E3V E3E E4X E4F I1V I2V I3V I3E
ALM M20k DSP fMAX (MHz)
Encoder N/A 13.3k 27 2 626 563 501 501 442 400 627 560 504 504
Dual Decoder LDPC2 Zmax=192 100.4k 1274 1 494 486 461 465 435 360 503 483 465 465
LDPC2 Zmax=192 using DSP 82.4k 1274 631 498 484 471 471 428 360 500 487 472 472
Single Decoder Standard 74.9k 908 1 500 488 468 468 435 362 499 489 471 470
Standard using DSP 60.4k 908 487 499 485 469 469 435 363 497 484 459 458
Lite 53.9k 601 1 519 489 444 444 424 338 502 482 446 446
Super Lite 41.0k 554 1 516 500 452 452 426 343 513 497 453 453
Table 4.  Performance and Resources for Arria® 10 10AT115S1F45E1SG, Stratix® 10-2L 1SG280HU2F50E2LG, and Stratix® 10-2 1SG280HU2F50E2VG DevicesAve fMAX (reduced 15% for margins in your designs)
Architecture Configuration 10AT115S1F45E1SG 1SG280HU2F50E2LG 1SG280HU2F50E2VG
ALMs M20K DSP Ave fMAX (MHz) ALMs M20K DSP Ave fMAX (MHz) ALMs M20K DSP Ave fMAX (MHz)
Encoder N/A 12.2k 27 1 334 12.1k 27 2 382 12.5k 27 2 409
Dual decoder LDPC2 Zmax=192 90.9k 1247 1 292 109.2k 1274 1 352 108.4k 1274 1 383
LDPC2 Zmax=192 using DSP 75.6k 1247 631 293 97.4k 1274 631 348 96.3k 1274 631 364
Single decoder Standard 67.4k 881 1 294 80.0k 908 1 366 79.4k 908 1 382
Standard using DSP 55.1k 881 487 302 71.5k 908 487 367 70.7k 908 487 378
Lite 52.8k 574 1 296 56.5k 601 1 343 56.5k 601 1 358
Super lite 39.8k 526 1 309 42.6k 554 1 379 42.6k 554 1 379
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