ASMI Parallel II Intel® FPGA IP User Guide

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ID 683669
Date 10/09/2023
Public
Document Table of Contents
Document Table of Contents x
ASMI Parallel II Intel® FPGA IP User Guide
ASMI Parallel II Intel® FPGA IP User Guide x
Release Information Ports Parameters Register Map Operations ASMI Parallel II Intel® FPGA IP Use Case Examples ASMI Parallel II Intel® FPGA IP User Guide Archives Document Revision History for the ASMI Parallel II Intel® FPGA IP User Guide
Operations x
Control Status Register Operations Memory Operations
ASMI Parallel II Intel® FPGA IP Use Case Examples x
Example 1: Read the Silicon ID of the Configuration Devices Example 2: Read and Write One Word of Data at Address H'40000000 Example 3: Erase Sector 64 Example 4: Perform Sector Protect at Sectors (0 to 127) Example 5: Read and Clear Flag Status Register Example 6: Read and Write nvcr
ASMI Parallel II Intel® FPGA IP User Guide

Example 6: Read and Write nvcr

#Bit 15:12 indicates number of dummy clock cycles
read_nvcr 
#Change dummy cycles to 8
write_nvcr 0x8fff
#Read back non-volatile configuration register to confirm the dummy cycles is 
#changed
read_nvcr
Level Two Title