AN 883: Intel Arria 10 DisplayPort TX-only Design

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ID 683597
Date 7/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort TX-only Design
1. Intel® Arria® 10 DisplayPort TX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the TX-only Design with Bitec FMC Daughter Card 1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Compiling and Testing the Design 1.4.3. Running the Hardware 1.4.4. Design Debug Features
1.4.2. Compiling and Testing the Design x
1.4.2.1. Regenerating ELF File
1.4.4. Design Debug Features x
1.4.4.1. Main Stream Attribute (MSA) Information 1.4.4.2. Auxiliary Channel Traffic Monitor
1.5. Creating the TX-only Design with Bitec FMC Daughter Card x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs 1.5.4. Generated Clocks 1.5.5. Making a Direct Connection to the TX Transceiver Block 1.5.6. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort TX-only Design

1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs

After removing irrelevant blocks in the design, instantiate the relevant Video and Image Processing FPGA IPs.
  1. Instantiate the Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II Intel® FPGA IPs in the Platform Designer and specify the parameters. The table below is an example of parameter value that generates a 4kp60 video.
    Note: The Test Pattern Generator (TPG) II Intel® FPGA IP generates video stream that displays color bars video pattern. The Clocked Video Output II Intel® FPGA IP converts the Avalon-ST video format received from the TPG II Intel® FPGA IP to standard clocked video format.
    Note: Certain sink devices may not be able to accept below video resolution and settings. Contact sink device manufacturer for more information.
    Table 7.  Clocked Video Output (CVO) II and Test Pattern Generator (TPG) II Parameter Settings
    FPGA IP Parameters Value
    Clocked Video Output II
    Note: The CVO II parameter setting is specific for 4K video resolution. For other video resolution, refer to VESA monitor timing standard specifications.
    		Image width / Active pixels 3840
    Image height / Active lines 2160
    Bits per pixel per color plane 10
    Number of color planes 3
    Number of pixels in parallel 4
    Separate syncs only - Frame/ Field 1 Horizontal sync 32
    Separate syncs only - Frame/ Field 1 Horizontal front porch 48
    Separate syncs only - Frame/ Field 1 Horizontal back porch 80
    Separate syncs only - Frame/ Field 1 Vertical sync 5
    Separate syncs only - Frame/ Field 1 Vertical front porch 3
    Separate syncs only - Frame/ Field 1 Vertical back porch 54
    Pixel FIFO size 3840
    FIFO level at which to start output 3839
    Use control port 4
    Test Pattern Generator II Bits per color sample 10
    Number of pixels in parallel 4
    Color planes transmitted in parallel Yes
    Output format 4:4:4
    Maximum frame width 3840
    Maximum frame height 2160
    Default Interlacing Progressive output
    Number of test patterns 1
    Pattern Color bars
    Subsampling & Colorspace RGB
  2. Add Clock Bridge (160MHz clock input to TPG II and CVO II) for VIP and export out the input port.
  3. Add Reset Bridge (active low reset with none synchronous edges) for VIP and export out the input port.
  4. Connect the CVO II and TPG II Intel® FPGA IP instances in the Platform Designer.
    Figure 6. Connecting the CVO II and TPG II in the Platform Designer
    Note: The CVO II and TPG II Intel® FPGA IPs share the reset input from the reset generator output. Ensure the Clocked Video Port of CVO II FPGA IP signals are exported out from Platform Designer.
  5. Save the changes, run Sync System Info & Validate System Integrity. After that, proceed to Generate HDL.
    Note: By adding TPG II, CVO II, Clock and Reset Bridge in the system, design top level instantiations of dp_core modules needs to be updated. Refer to the Instantiation Template in Platform Designer and update your top level instantiation accordingly.
    Note: Ensure the TPG II, CVO II, Clock and Reset Bridge are listed in the Quartus Project Navigator. If it is not available, manually add the IPs in the Quartus Settings > Files.
  6. At the top level design file, connect the signals in the DisplayPort TX sub-system as shown below.
    Figure 7. Video PLL with Tx_vid_clk output
    Note: The CVO II and TPG II Intel® FPGA IPs share the reset input from the reset generator output (reset_n), through VIP Reset Bridge.
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