CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/17/2024
Public
Document Table of Contents

2.2. Generating aCPRI Intel® FPGA IP

You specify CPRI IP options and parameters in the parameter editor to generate a custom Intel® FPGA IP variation
Figure 4. IP Parameter Editor
  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device. In the Quartus® Prime Standard Edition software, this step is not required.
  2. In the Intel® FPGA IP Catalog (Tools > IP Catalog), locate and double-click the name CPRI Intel FPGA IP. The parameter editor appears.
  3. Specify a top-level name for your custom Intel® FPGA IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip (in Quartus® Prime Pro Edition) or <your_ip>.qsys (in Quartus® Prime Standard Edition). Click OK.
  4. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to CPRI Intel FPGA IP Core Parameters for information about specific IP parameters.
    • Specify parameters defining the IP core functionality, port configurations, and device-specific features.
    • Specify options for processing the IP core files in other EDA tools.
  5. Click Generate HDL. The Generation dialog box appears.
  6. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
  7. To generate a simulation testbench: click Generate Example Design.
    • For simulation, refer to the instructions in the Running the Testbench section.
    • For synthesis, for Agilex™ 7 F-Tile, select device AGIB027R31B1E2V when generating hardware design example with Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit.
    Note: To generate a design example with line bit rate auto-negotiation option (Enable line bit rate auto-negotiation), you must also select the option Enable Auto Rate Negotiation ED.
  8. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
  9. Click Finish. The parameter editor adds the top-level .qsys or .ip file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.
    For Agilex® 7 F-tile devices:
    1. Copy the cpri_ii_tile_ip_gen.tcl from <your_ip>/altera_cpri_ii_c2p_top_<c2p version>/sim/ or <your_ip>/altera_cpri_ii_c2p_top_<c2p_version>/synth/ into the same level as <your_ip>.ip
    2. Execute this file using:
      quartus_sh -t cpri_ii_tile_ip_gen.tcl <your_ip> skip_qtlg
    Few IPs are generated along a top-level wrapper. The wrapper intel_cpri_wrapper.v is the top-level file for this IP. The systemclk_f_inst.ip, iopll_sclk_inst.ip, dr_ctrl_inst.ip (generated when rate negotiation is enabled), and cpriphy_ftile_0.ip are the generated IPs. You must add all these files manually to your Quartus® Prime project.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.