CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/17/2024
Public
Document Table of Contents

2.8. CPRI Design Example Clocks

To run the testbench or synthesizable hardware design example on the supported devices, you must supply the appropriate clock top level (tb_top) input ports with fixed frequencies:

  • clk_100: 100MHz
  • sampling_refclk: 100MHz (Only for the Agilex® 7 F-Tile devices)
  • cdr_refclk:
    • Supply clock with frequency for initial bit rate chosen according to the folllowing table, except for E-Tile, F-tile, and Agilex™ 5 devices.
    • Supply 153.60MHz clock for E-Tile, F-tile and Agilex™ 5 devices. when the IP's Core clock source input is External when generating the example design..
  • cdr_refclk1: Supply secondary clock with frequency for target bit rate according to the folllowing table (Only for the Stratix® 10 H-Tile or Arria® 10 devices when the Rate Negotiation feature is enabled).
    • If selected target bit rate for rate negotiation uses the same reference clock frequency as initial bit rate, supply cdr_refclk and cdr_refclk1 with the same clock frequency.
    • If one or more selected target bit rate for rate negotiation uses different reference clock frequency as initial bit rate, supply cdr_refclk with the frequency required for initial bit rate and supply cdr_refclk1 with the different secondary frequency.
  • ehip_ref_clk: Supply clock with frequency for initial bit rate chosen according to the folllowing table (Only for F-Tile and E-Tile devices).
  • ehip_ref_clk1: Supply secondary clock with frequency for target bit rate according to the folllowing table (Only for F-Tile and E-Tile devices when Rate Negotiation feature is enabled).
    • If selected target bit rate for rate negotiation uses the same reference clock frequency as initial bit rate, supply ehip_ref_clk and ehip_ref_clk1 with the same clock frequency.
    • If one or more selected target bit rate for rate negotiation uses different reference clock frequency as initial bit rate, supply ehip_ref_clk with the frequency required for initial bit rate and supply ehip_ref_clk1 with the different secondary frequency.
  • aib_pll_refclk: 156.25MHz (Only for F-Tile and E-Tile devices).
  • dr_clk_100G_hz: In the Agilex® 7 F-tile devices, this clock is dedicated only for simulation to speed up the NIOS in the dynamic reconfiguration controller. The clock is connected to i_cpu_clk port of the dynamic reconfiguration controller. The two clocks in the dynamic reconfiguration controller are driven as:
    • In design example simulation, i_cpu_clk = 100GHz and i_csr_clk = 100MHz
    • In hardware design example, i_cpu_clk = 100MHz and i_csr_clk = 100MHz
  • i_refclk_syspll: 153.6 MHz. Only for Agilex™ 5 devices.

    i_refclk_xcvr: supply clock with frequency for initial bit rate chosen according to the table. Only for Agilex™ 5 devices).

Table 18.  Reference Clock Frequency Requirement
Initial or Target Bit rate (Mbits/s) i_refclk_xcvr for Agilex™ 5 Devices (MHz) ehip_ref_clk and ehip_ref_clk1 for F-Tile and E-Tile Device (MHz) Other Device (MHz)
24330.24 Unsupported 184.32 253.44
12165.12 184.32 253.44
10137.60 184.32 184.32 253.44
9830.40 Unsupported 153.60 245.76
8110.08 184.32 253.44
6144.00 153.60 245.76
4915.20 153.60 153.60 245.76
3072.00 153.60 245.76
2457.60 153.60 245.76
1228.80 153.60 245.76
614.40 Unsupported 153.60 245.76