eCPRI Intel® FPGA IP Release Notes

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ID 683570
Date 9/30/2024
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1. eCPRI Intel® FPGA IP Release Notes
1. eCPRI Intel® FPGA IP Release Notes x
1.1. eCPRI Intel® FPGA IP v3.0.3 1.2. eCPRI Intel® FPGA IP v3.0.2 1.3. eCPRI Intel® FPGA IP v3.0.1 1.4. eCPRI Intel® FPGA IP v3.0.0 1.5. eCPRI Intel® FPGA IP v2.0.4 1.6. eCPRI Intel® FPGA IP v2.0.3 1.7. eCPRI Intel® FPGA IP v2.0.1 1.8. eCPRI Intel® FPGA IP v2.0.0 1.9. eCPRI Intel® FPGA IP v1.4.1 1.10. eCPRI Intel® FPGA IP v1.4.0 1.11. eCPRI Intel® FPGA IP v1.3.0 1.12. eCPRI Intel® FPGA IP v1.2.0 1.13. eCPRI Intel® FPGA IP v1.1.0 1.14. eCPRI Intel® FPGA IP v1.0.0 1.15. eCPRI Intel FPGA IP User Guide Archives 1.16. eCPRI Intel® FPGA IP Design Example User Guide Archives
1. eCPRI Intel® FPGA IP Release Notes

1.8. eCPRI Intel® FPGA IP v2.0.0

Table 8.  v2.0.0 2022.08.26
Quartus® Prime Version Description Impact
22.2 Added support for L2 CoS priority packet arbitration scheme based on the O-RAN Control, User and Synchronization Plane Specification 7.01 (ORAN-WG4.CUS.0-v07.01), Section 5.3 Quality of Service. —
Added support for Data Flow Identification mechanism based on the O-RAN Control, User and Synchronization Plane Specification 7.01 (ORAN-WG4.CUS.0-v07.01), Section 5.4 Data Flow Identification. —
Added new signal:
  • tx_queue_<N>_fifo_full
  • ext_source_pkt_type
  • ext_tx_ingress_timestamp_96b_data
  • ptp_tx_ingress_timestamp_96b_data
—
Added new IP parameters:
  • Default VLAN ID
  • Data Flow Maching Mechanism
  • Packets Arbitration Scheme
  • TX Packets Default Priority
  • TX Arbitration Queue 0 Depth
  • TX Arbitration Queue 1 Depth
  • TX Arbitration Queue 2 Depth
  • TX Arbitration Queue 3 Depth
  • TX Arbitration Queue 4 Depth
  • TX Arbitration Queue 5 Depth
  • TX Arbitration Queue 6 Depth
  • TX Arbitration Queue 7 Depth
—
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