Native Fixed Point DSP Agilex™ FPGA IP Core Release Notes

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ID 683569
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Native Fixed Point DSP Agilex™ 5 FPGA IP Release Notes 2. Native Fixed Point DSP Agilex™ 7 FPGA IP Release Notes
1. Native Fixed Point DSP Agilex™ 5 FPGA IP Release Notes x
1.1. Native Fixed Point DSP Agilex™ 5 FPGA IP v2.0.0 1.2. Native Fixed Point DSP Agilex™ 5 FPGA IP v1.0.0
2. Native Fixed Point DSP Agilex™ 7 FPGA IP Release Notes x
2.1. Native Fixed Point DSP Agilex™ 7 FPGA IP v19.1.1
1. Native Fixed Point DSP Agilex™ 5 FPGA IP Release Notes
2. Native Fixed Point DSP Agilex™ 7 FPGA IP Release Notes

1.1. Native Fixed Point DSP Agilex™ 5 FPGA IP v2.0.0

Table 1.  v1.0.0 2024.07.08
Quartus® Prime Version Description Impact
24.2 Added registers:
  • sub_systolic_reg
  • negate_systolic_reg
IP upgrade is required to include new registers.
Level Two Title