Agilex™ 7 Hard Processor System Technical Reference Manual

ID 683567
Date 8/13/2024
Public
Document Table of Contents

C.3. Signal Behavior Event Diagrams

The following sections show diagrams which describe the behavior of the signals. These diagrams are not cycle accurate but they are relationally accurate. You can see that h2f_gp_out[1] goes low which allows specific FPGA application logic to remain in reset while the events are occurring. Then you can see that h2f_gp_out[1] goes high, controlled by HPS software, when it is safe to release the specific FPGA application logic from reset, to begin interaction with the HPS.

The following diagrams show the use of h2f_user0_clock and h2f_gp_out[1], but designs can easily use h2f_user1_clock and any of the h2f_gp_out[31:0] signals. Also, the “CPU is operational” row is not a signal, but merely an indication when the CPU is executing software code.