Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

Download PDF
ID 683551
Date 4/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 2.1.4. Compiling and Configuring the Design Example in Hardware
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench x
2.1.3.1. Procedure
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Hardware Testing 2.2.6. Interface Signals 2.2.7. Configuration Registers
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clocking Scheme
2.2.5. Hardware Testing x
2.2.5.1. Test Procedure
2.2.7. Configuration Registers x
2.2.7.1. Register Access Definition 2.2.7.2. Triple-Speed Ethernet Register Map 2.2.7.3. Traffic Controller Register Map 2.2.7.4. TOD Register Map
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

2.2.5.1. Test Procedure

Follow these steps to test the design example in hardware:

  1. Launch the Quartus® Prime Pro Edition software and open the design example project file. Select Processing > Start Compilation to compile the design example. The timing constraints for the design example and the design components are automatically loaded during compilation.
    Note: Pin-out changes are required depending on the revision of the Stratix® 10 TX Signal Integrity Development Kit that is used for hardware testing.

    For engineering sample (ES) edition (Revision A) board, no changes is required as the TX and RX serial data pins are connected to the QSFP-DD ports.

    For production edition (Revision B) board, update the pin-outs in the QSF file to connect the TX and RX serial data pins to the QSFP-DD ports, as shown below.
    1. tx_serial_data: PIN_AT54 -to PIN_AU4
    2. rx_serial_data: PIN_AT48 -to PIN_AU10
    3. refclk_1g: PIN_AN42 -to PIN_AN13
  2. Connect the development board to the host computer.
  3. Launch the Clock Control application, which is part of the development kit, and set the respective clock frequencies required by the design.
  4. In the Quartus® Prime Pro Edition software, select Tools > Programmer to configure the FPGA on the development board using the generated .sof file.
  5. In the Quartus® Prime Pro Edition software, select Tools > In-System Sources and Probes Editor. Set the Source[0] to 1 to release the reset for the system, as shown in the figure below.
    Figure 17. In-System Sources and Probes Editor Setting
  6. In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  7. Change the working directory to <Example Design>\hardware_test_design\sc.
  8. Initialize the design command list by running this command: 
    source main.tcl
  9. Run the following loopback test from the System Console:
    TEST_SMA_LB <channel> <speed> <burst_size>
    For example: 
    TEST_SMA_LB 0 1G 1000
  10. When the test is completed, observe the output displayed.
    Figure 18. Sample Test Output—Ethernet Packet MonitorThis figure shows the Ethernet packet monitor block receives the same number of packets generated without error.
    Figure 19. Sample Test Output—TX and RX Statistics Counters
Level Two Title