Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

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ID 683551
Date 4/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 2.1.4. Compiling and Configuring the Design Example in Hardware
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench x
2.1.3.1. Procedure
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Hardware Testing 2.2.6. Interface Signals 2.2.7. Configuration Registers
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clocking Scheme
2.2.5. Hardware Testing x
2.2.5.1. Test Procedure
2.2.7. Configuration Registers x
2.2.7.1. Register Access Definition 2.2.7.2. Triple-Speed Ethernet Register Map 2.2.7.3. Traffic Controller Register Map 2.2.7.4. TOD Register Map
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

2.2.7.2. Triple-Speed Ethernet Register Map

This topic lists the byte offsets of the Triple-Speed Ethernet registers used in the design example. Refer to the Triple-Speed Ethernet Intel® FPGA IP User Guide for the descriptions of the registers.
Table 13.  Base Configuration Register Map for Triple-Speed Ethernet Intel® FPGA IP
Byte Offset R/W Name HW Reset
0x00 RO rev_address <IP version number>
0x04 RW mac_scratch_address 0
0x08 RW command_config_address 0
0x0C RW mac_0_address 0
0x10 RW mac_1_address 0
0x14 RW frm_length_address 1518
0x5C RW tx_ipg_length_address 0
Table 14.  Statistics Counters for Triple-Speed Ethernet Intel® FPGA IP
Byte Offset R/W Name HW Reset
0x60 RO aMacID_0 0
0x64 RO aMacID_1 0
0x68 RO aFramesTransmittedOK 0
0x6C RO aFramesReceivedOK 0
0x70 RO aFrameCheckSequenceErrors 0
0x74 RO aAlignmentErrors 0
0x78 RO aOctetsTransmittedOK 0
0x7C RO aOctetsReceivedOK 0
0x80 RO aTxPAUSEMACCtrlFrames 0
0x84 RO aRxPAUSEMACCtrlFrames 0
0x88 RO ifInErrors 0
0x8C RO ifOutErrors 0
0x90 RO ifInUcastPkts 0
0x94 RO ifInMulticastPkts 0
0x98 RO ifInBroadcastPkts 0
0xA0 RO ifOutUcastPkts 0
0xA4 RO ifOutMulticastPkts 0
0xA8 RO ifOutBroadcastPkts 0
0xAC RO etherStatsDropEvents 0
0xB0 RO etherStatsOctets 0
0xB4 RO etherStatsPkts 0
0xB8 RO etherStatsUndersizePkts 0
0xBC RO etherStatsOversizePkts 0
0xC0 RO etherStatsPkts64Octets 0
0xC4 RO etherStatsPkts65to127Octets 0
0xC8 RO etherStatsPkts128to255Octets 0
0xCC RO etherStatsPkts256to511Octets 0
0xD0 RO etherStatsPkts512to1023Octets 0
0xD4 RO etherStatsPkts1024to1518Octets 0
0xD8 RO etherStatsPkts1519toXOctets 0
0xDC RO etherStatsJabbers 0
0xE0 RO etherStatsFragments 0
Table 15.  IEEE 1588v2 MAC Registers for Triple-Speed Ethernet Intel® FPGA IP
Byte Offset R/W Name HW Reset
0x340 RW tx_1g_period_addr 0
0x344 RW tx_1g_adjust_fns_addr 0
0x348 RW tx_1g_adjust_ns_addr 0
0x34C RW rx_1g_period_addr 0
0x350 RW rx_1g_adjust_fns_addr 0
0x354 RW rx_1g_adjust_ns_addr 0
Table 16.  PCS Configuration Registers for Triple-Speed Ethernet Intel® FPGA IP
Byte Offset R/W Name HW Reset
0x00 RW tse_pcs_control_address 0x1140
0x04 RO tse_pcs_status_address 0x0089
0x08 RO tse_pcs_phy_id_0_address 0x0101
0x0C RO tse_pcs_phy_id_1_address 0x0101
0x10 RW tse_pcs_dev_ability_address 0x01A0
0x14 RO tse_pcs_partner_ability_address 0
0x18 RW tse_pcs_an_expansion_address 0
0x40 RW tse_pcs_scratch_address 0
0x44 RO tse_pcs_revision_address <IP version number>
0x48 RW tse_pcs_link_timer0_address 0x8968
0x4C RW tse_pcs_link_timer1_address 0x0009
0x50 RW tse_pcs_if_mode_address 0
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