Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

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ID 683551
Date 4/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver 3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
1.1. Quick Start Guide 1.2. Design Example Description
1.1. Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design Example 1.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.1.4. Compiling and Configuring the Design Example in Hardware
1.1.2. Generating the Design Example x
1.1.2.1. Design Example Parameters
1.2. Design Example Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Functional Description 1.2.4. Simulation 1.2.5. Hardware Testing 1.2.6. Interface Signals
1.2.3. Functional Description x
1.2.3.1. Design Components
1.2.4. Simulation x
1.2.4.1. Testbench
1.2.5. Hardware Testing x
1.2.5.1. Test Procedure
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver x
2.1. Quick Start Guide 2.2. Design Example Description
2.1. Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design Example 2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 2.1.4. Compiling and Configuring the Design Example in Hardware
2.1.2. Generating the Design Example x
2.1.2.1. Design Example Parameters
2.1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench x
2.1.3.1. Procedure
2.2. Design Example Description x
2.2.1. Features 2.2.2. Hardware and Software Requirements 2.2.3. Functional Description 2.2.4. Simulation 2.2.5. Hardware Testing 2.2.6. Interface Signals 2.2.7. Configuration Registers
2.2.3. Functional Description x
2.2.3.1. Design Components 2.2.3.2. Clocking Scheme
2.2.5. Hardware Testing x
2.2.5.1. Test Procedure
2.2.7. Configuration Registers x
2.2.7.1. Register Access Definition 2.2.7.2. Triple-Speed Ethernet Register Map 2.2.7.3. Traffic Controller Register Map 2.2.7.4. TOD Register Map
1. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
2. 10/100/1000Mb Ethernet MAC (Fifoless) Design Example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB Transceiver
3. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

2.1.1. Directory Structure

The Triple-Speed Ethernet Intel® FPGA IP design example file directories contain the following generated files for the 10/100/1000Mb Ethernet MAC (Fifoless) design example with IEEE1588v2 and 1000BASE-X/SGMII 2XTBI PCS with E-tile GXB transceiver:
  • The compilation and hardware design example, hardware configuration, and test files are located in <design_example_dir>/hardware_test_design.
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
Figure 11. Directory Structure for the Design Example
Table 7.  Directory and File Description
Directory/File Description
altera_eth_top.qpf Quartus® Prime Pro Edition project file.
altera_eth_top.qsf Quartus® Prime Pro Edition settings file.
altera_eth_top.sv Design example top-level HDL.
altera_eth_top.sdc Synopsys Design Constraints (SDC) file.
common The folder that contains the design example components such as address decoder and traffic controller.
ip The folder that contains the design example synthesizable components including Platform Designer generated IPs, such as TSE, IOPLL, Native PHY, and JTAG.
sc The folder that contains system console scripts for hardware testing.
top/alt_mge_multi_channel.sv

top/alt_mge_channel.v

Design example DUT top-level files.
output_files The folder that contains Quartus® Prime Pro Edition output files including Quartus® Prime Pro Edition compilation reports and design programing file (.sof file).
example_testbench/models The folder that contains the testbench files.
example_testbench/mentor

example_testbench/synopsys/vcs

example_testbench/synopsys/vcsmx

example_testbench/xcelium

The folder that contains the simulation script. It also serves as a working area for the simulator.
Level Two Title