RapidIO II Intel® FPGA IP Release Notes

Download PDF
ID 683549
Date 9/28/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. RapidIO II Intel® FPGA IP Release Notes
1. RapidIO II Intel® FPGA IP Release Notes x
1.1. RapidIO II IP v19.2.0 1.2. RapidIO II Intel® FPGA IP v18.0 1.3. RapidIO II IP Core v17.1 1.4. RapidIO II IP Core v15.1 1.5. RapidIO II IP Core v14.1 1.6. RapidIO II IP Core v14.0 Arria 10 Edition 1.7. RapidIO II IP Core v14.0 1.8. RapidIO II IP Core v13.1 1.9. RapidIO II IP Core v13.0 1.10. RapidIO II IP Core User Guide Archives
Product Discontinuance Notification
1. RapidIO II Intel® FPGA IP Release Notes

1.5. RapidIO II IP Core v14.1

Table 5.  Version 14.1 December 2014
Description Impact Note
The Quartus II software v14.1 requires that you specify a device if your IP core targets the Arria 10 device family. If you do not specify your target Arria 10 device, the IP Upgrade tool insists that your IP core requires upgrade, but does not clarify the reason. You must ensure that you specify a device for your v14.0 Arria 10 Edition IP core variation and regenerate it in the Quartus II software v14.1. —
Added io_error_response_set input port. The IP core sets the IO_ERROR_RSP field in bit [31] of the Logical/Transport Layer Error Detect CSR at offset 0x308 when this signal changes value from 0 to 1. If you upgrade the RapidIO II IP core in your design to the IP core v14.1, you must reconnect the IP core in your design so the new input signal does not float. —
Changed behavior of individual baud rate _ENABLE and _SUPPORT fields of Port 0 Control 2 CSR at offset 0x154. Instead of all being set to the value of 1, now the _SUPPORT fields for baud rates less than or equal to the value of the Maximum baud rate parameter have the value of 1, and the _SUPPORT fields for baud rates greater than the value of the Maximum baud rate parameter have the value of 0. Instead of all being set to the value of 1, now the _ENABLE field for the baud rate at which the IP core is operating has the value of 1, and the _ENABLE fields for all other baud rates have the value of 0. If you upgrade the RapidIO II IP core in your design to the IP core v14.1, the Port 0 Control 2 CSR fields are set as expected to indicate the supported and enabled baud rates. To modify the IP core to run at a different baud rate than the Maximum baud rate value, you must turn on Enable transceiver dynamic reconfiguration in the parameter editor, and user logic must reconfigure the transceiver to the new baud rate. As indicated by the values of the Port 0 Control 2 CSR fields, you can only reconfigure the IP core to a baud rate equal or slower than the Maximum baud rate value.
Made changes to Port 0 Control CSR at offset 0x15C:
  • Added new field PORT_ERR_IRQ_EN that controls whether an interrupt is generated when an error is flagged in the Port 0 Error Detect register at offset 0x340. The new field is in bit [6] of the Port 0 Control CSR.
  • Moved DIS_DEST_ID_CHK field from bit [7] to bit [8].
  • Moved LOG_TRANS_ERR_IRQ_EN field from bit [6] to bit [7].
If you upgrade the RapidIO II IP core in your design to the IP core v14.1, your IP core implements the new behavior. You can use the new register field to force an interrupt in this case. —
Related Information
Level Two Title